DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 174 of 242
Field
Description of fields within Sub-Register 0x2C:0A – AON_CFG1
(b) Set this LPOSC_CAL bit to 1, and upload it into the AON block by toggling the UPL_CFG
bit (in AON_CTRL) to 1 and back to 0.
(c) Clear the LPOSC_CAL bit to 0, and upload it into the AON block by toggling UPL_CFG (in
AON_CTRL) to 1 and back to 0.
(d) Force the system clock to be the 19.2 MHz XTI clock, by setting SYSCLKS (in
) to 01 (binary).
(e) Wait for 400 µs to ensure a calibration count value is available. This is a 16-bit value
counting how many clock periods of the 19.2 MHz XTI clock it took to complete one
complete period of the low power ring oscillator.
(f) The ring oscillator period counter’s 8 MSBs are accessed at AON memory address 118
decimal (0x76) and its 8 LSBs are accessed at AON memory address 117 decimal (0x75).
Please refer to in section
7.2.45.4 – Reading from a specified address within AON
for details of the procedure defined for reading AON memory.
(g) After reading the period counter, restore the system clock automatic mode by setting
the SYSCLKS configuration back to 0.
The operating frequency of the ring oscillator is given by 19.2 MHz divided by the period
counter value.
–
reg:2C:0A
bits:15–3
Reserved bits
7.2.46 Register file: 0x2D
– OTP Memory Interface
ID
Length
(octets)
Type
Mnemonic
Description
0x2D
-
-
OTP_IF
One Time Programmable Memory Interface
register file 0x2D is the OTP memory interface. This allows read access to parameters stored in
the OTP memory, and it is also the interface via which parameters are programmed into the OTP memory.
The OTP memory interface contains a number of sub-registers. An overview of these sub-registers is given
by Table 47, and each is then separately described in the sub-sections below.
NOTE: Programming OTP memory is a one-time only activity, any values programmed in error cannot be
corrected. Also, please take care when programming OTP memory to only write to the designated areas –
programming elsewhere may permanently damage the DW1000’s ability to function normally.
For more details of the OTP memory please refer to section
6.3 – Using the on-chip OTP memory
Table 47: Register file: 0x2D – OTP Memory Interface overview
OFFSET in Register 0x2D
Mnemonic
Description
OTP Write Data
OTP Address
OTP Control
OTP Status
OTP Read Data
