DEC Digital Alpha VME 4/224 User Manual Download

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6.5

Address Space of Control/Status Registers . . . . . . . . . . . . .

6–8

6.6

Description of CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–11

6.6.1

General Control Register . . . . . . . . . . . . . . . . . . . . . . .

6–11

6.6.2

Error and Diagnostic Status Register . . . . . . . . . . . . .

6–13

6.6.3

Tag Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–16

6.6.4

Error Low Address Register . . . . . . . . . . . . . . . . . . . . .

6–18

6.6.5

Error High Address Register . . . . . . . . . . . . . . . . . . . .

6–19

6.6.6

LDx_L Low Address Register . . . . . . . . . . . . . . . . . . . .

6–19

6.6.7

LDx_L High Address Register . . . . . . . . . . . . . . . . . . .

6–20

6.6.8

Memory Control Registers . . . . . . . . . . . . . . . . . . . . . .

6–20

6.6.8.1

Presence Detect Low-Data Register . . . . . . . . . . . .

6–20

6.6.8.2

Presence Detect High-Data Register . . . . . . . . . . .

6–21

6.6.8.3

Base Address Registers . . . . . . . . . . . . . . . . . . . . .

6–21

6.6.8.4

Configuration Registers . . . . . . . . . . . . . . . . . . . . .

6–22

6.6.8.5

Bank Set Timing Registers . . . . . . . . . . . . . . . . . .

6–24

6.6.8.6

Global Timing Register . . . . . . . . . . . . . . . . . . . . .

6–27

6.6.8.7

Refresh Timing Register . . . . . . . . . . . . . . . . . . . .

6–28

6.7

Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–30

6.7.1

Memory Read Buffer . . . . . . . . . . . . . . . . . . . . . . . . . .

6–31

6.7.2

I/O Read Buffer and Merge Buffer . . . . . . . . . . . . . . . .

6–31

6.7.3

I/O Write and DMA Read Buffer . . . . . . . . . . . . . . . . .

6–31

6.7.4

DMA Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–31

6.7.5

Memory Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . .

6–32

6.7.6

Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–32

7 PCI Host Bridge

7.1

Interface to the System Bus . . . . . . . . . . . . . . . . . . . . . . . .

7–2

7.1.1

Decoding Physical Addresses . . . . . . . . . . . . . . . . . . . .

7–2

7.1.2

Buffering System Bus Transactions . . . . . . . . . . . . . . .

7–3

7.1.3

Burst Length and Prefetching for the System Bus . . . .

7–3

7.2

Interface to the PCI bus . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3

7.2.1

Decoding PCI Addresses . . . . . . . . . . . . . . . . . . . . . . .

7–3

7.2.2

Buffering PCI Transactions . . . . . . . . . . . . . . . . . . . . .

7–3

7.2.3

Burst Length and Prefetching for PCI bus . . . . . . . . . .

7–4

7.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4

7.3.1

Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4

7.3.2

Parity Support

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4

7.3.3

Data Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5

7.3.4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6

7.3.5

Exclusive Access

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6

7.3.6

Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6

7.3.7

Retry Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7

Summary of Contents for Digital Alpha VME 4/224

Page 1: ...4 module It provides configuration and installation procedures and describes the module s built in features including the console code and diagnostics Revision Update Information This manual supersedes the Digital Alpha VME 4 224 and 4 288 Single Board Computers User Guide and Technical Description EK DAVME TD A01 Digital Equipment Corporation Maynard Massachusetts ...

Page 2: ...ten in welchen Fällen der Benutzer für entsprechende Gegenmaßnahmen verantwortlich ist Attention Ceci est un produit de Classe A Dans un environment domestique ce produit risque de créer des interférences radioélectriques il appartiendra alors à l utilisateur de prendre les mesures spécifiques appropriées Canadian EMC Notice This Class A Digital apparatus meets all requirements of the Canadian Int...

Page 3: ... Card 2 23 2 3 Diagnostics 2 27 2 4 Troubleshooting 2 29 2 5 Repair and Warranty Information 2 32 2 5 1 Return to Digital Hardware Maintenance 2 32 2 5 2 Hardware Warranty 2 32 2 5 2 1 Availability 2 32 2 5 2 2 Return to Digital Process 2 33 2 5 2 3 Response Time 2 33 2 5 2 4 Eligible Parts 2 33 2 5 2 5 Purchaser Responsibility 2 33 2 5 2 6 Pre Call Checklist 2 34 2 5 3 Software Maintenance 2 34 2...

Page 4: ...gnostic Test Descriptions 4 2 4 3 1 Available Console Diagnostics 4 2 4 3 2 SROM Initialization Countdown 4 4 4 3 3 Console POST Descriptions 4 5 POST Non Volatile RAM Diagnostic 4 6 POST Memory Diagnostic 4 7 4 3 4 Console Diagnostic Test Descriptions 4 8 Heartbeat Timer Test 4 9 Interval Timer Tests 4 10 DECchip 21040 Ethernet Controller Tests 4 16 DALLAS DS1386 RAMified Watchdog Timekeeper Test...

Page 5: ...ation Cycles to Primary Bus Targets 5 9 5 1 7 2 PCI Configuration Cycles to Secondary Bus Targets 5 10 5 1 8 PCI Sparse Memory Space 0x200000000 to 0x2FFFFFFFF 5 11 5 1 9 PCI Dense Memory Space 0x300000000 to 0x3FFFFFFFF 5 14 5 2 PCI to Physical Memory Addressing 5 15 6 Cache and Memory Subsystem 6 1 System Bus Interface 6 4 6 1 1 Arbitration on the System Bus 6 4 6 1 2 System Bus Controller 6 4 6...

Page 6: ...iming Register 6 27 6 6 8 7 Refresh Timing Register 6 28 6 7 Data Path 6 30 6 7 1 Memory Read Buffer 6 31 6 7 2 I O Read Buffer and Merge Buffer 6 31 6 7 3 I O Write and DMA Read Buffer 6 31 6 7 4 DMA Write Buffer 6 31 6 7 5 Memory Write Buffer 6 32 6 7 6 Error Handling 6 32 7 PCI Host Bridge 7 1 Interface to the System Bus 7 2 7 1 1 Decoding Physical Addresses 7 2 7 1 2 Buffering System Bus Trans...

Page 7: ... PCI Master Latency Timer Register 7 20 7 5 12 TLB Tag Registers 0 Through 7 7 20 7 5 13 TLB Data Registers 0 Through 7 7 21 7 5 14 Translation Buffer Invalidate All Register 0x1A0000400 7 22 8 PCI bus 8 1 Ethernet Controller 8 3 8 1 1 PCI Configuration Registers 8 3 8 1 2 Ethernet Controller CSRs 8 4 8 1 3 PCI Cycles 8 5 8 1 4 Ethernet Address 8 6 8 2 SCSI Controller 8 6 8 2 1 Connection and Term...

Page 8: ...9 6 TOY Clock 9 22 9 6 1 TOY Clock Timekeeping Registers 9 23 9 6 2 TOY Clock Command Register 9 24 9 7 Interval Timing Registers 9 25 9 7 1 Interval Timing Control Register 9 26 9 7 2 Timer Registers 9 28 9 7 3 Timer Modes 9 29 9 7 4 Interrupts 9 31 9 7 5 Timer Interrupt Status Registers 9 32 9 8 Watchdog Timer 9 33 9 9 Nonvolatile RAM 9 36 10 VME Interface 10 1 VMEbus Master 10 2 10 1 1 Outbound...

Page 9: ... VME Interface 10 30 10 5 1 VME PCI Configuration Registers 10 30 10 5 2 Programming Scatter Gather RAM 10 31 10 5 3 Configuring the VIC64 10 32 10 6 Summary of VME Interface Registers 10 37 10 7 VME Subsystem Restrictions as of 03 Jun 94 10 40 10 7 1 Collision of VIC64 Master Write Posting with Master Block Transfers 10 40 10 7 2 VIC64 Errata A16 Master Cycles During Interleave 10 40 11 System In...

Page 10: ... 12 10 12 5 Using Pipes and grep to Filter Output 12 12 12 6 Using I O Redirection 12 12 12 7 Running Commands in Background 12 13 12 7 1 Monitoring Status 12 13 12 7 2 Killing a Process 12 14 12 8 Creating Scripts 12 14 12 9 Copying Scripts Over the Network 12 15 13 Console Commands 13 1 Console Commands 13 1 13 1 1 Special Keys 13 1 13 1 2 Command Line Characteristics 13 2 13 1 3 Radix Control 1...

Page 11: ...13 60 kill 13 61 line 13 62 ls 13 63 memexer 13 64 memtest 13 65 net 13 72 ps 13 75 pwrup 13 76 rm 13 77 sa 13 78 semaphore 13 79 set 13 80 set led 13 83 set reboot srom 13 84 set toy sleep 13 85 sh 13 86 show 13 88 show config 13 90 show device 13 91 show hwrpb 13 93 show led 13 94 show map 13 95 show_log 13 96 sleep 13 98 sort 13 99 xi ...

Page 12: ...9 Index Figures 1 1 Digital Alpha VME 4 Block Diagram 1 3 2 1 Digital Alpha VME 4 Module Components 2 2 2 2 Digital Alpha VME 4 Module Layout 2 7 2 3 I O Module Layout 2 8 2 4 Installing the Main Memory Modules 2 11 2 5 Cache Memory Modules 2 13 2 6 Installing the Digital Alpha VME 4 Module 2 15 2 7 Alpha VME 4 Primary Breakout Module 2 16 2 8 Primary Breakout Module Jumpers 2 17 2 9 Connecting th...

Page 13: ...Paths of Cache and Memory 6 2 6 3 21071 CA Block Diagram 6 3 6 4 Cache Subsystem for a 2 MB Cache 6 5 6 5 Maximum and Minimum DIMM Bank Layouts 6 6 6 6 General Control Register 0x180000000 6 11 6 7 Error and Diagnostic Status Register 0x180000020 6 14 6 8 Tag Enable Register 0x180000060 6 16 6 9 Error Low Address Register 0x180000080 6 19 6 10 Error High Address Register 0x1800000A0 6 19 6 11 LDx_...

Page 14: ... 2 0x1A00001C0 7 19 7 12 PCI Master Latency Timer Register 0x1A00001E0 7 20 7 13 TLB Tag Registers 0 Through 7 0x1A0000200 to 0x1A00002E0 7 21 7 14 TLB Data Registers 0 Through 7 0x1A0000300 to 0x1A00003E0 7 21 8 1 PCI Bus and Interfaces to the I O Subsystem 8 2 8 2 PCI Configuration Registers 8 4 8 3 DECchip 21040 AA CSR9 ENET ROM Register 8 6 8 4 PCI Configuration Block 8 8 9 1 Nbus and Nbus Res...

Page 15: ... Gather Entry With A32 Address Mapping 10 12 10 10 VME Interface Processor Page Monitor CSR 10 13 10 11 VIC Arbiter Requester Configuration Register 10 18 10 12 VIC Release Control Register 10 20 10 13 VMEbus Transfer Timeout Register 10 22 10 14 VIC Interrupt Request Status Register 10 24 10 15 VMEbus Interrupt Vector Base Registers 10 25 10 16 VMEbus Interrupter Interrupt Control Register 10 25 ...

Page 16: ...r Supply Current and Module Power Dissipation 1 5 2 1 Digital Alpha VME 4 Hardware Kit Items 2 3 2 2 Digital Alpha VME 4 Memory Modules 2 4 2 3 Digital Alpha VME 4 Cache Memory Modules 2 4 2 4 Additional Hardware Installation Items 2 5 2 5 Digital Alpha VME 4 Module Configuration Switches 2 9 2 6 Supported Switch Settings for Digital Alpha VME 4 Modules in Slot 1 System Controller 2 9 2 7 Supporte...

Page 17: ...Cache Size Tag Enable Values 6 17 6 5 Maximum Memory Tag Enable Values 6 18 6 6 Configuration Register for Banks 0 and 1 6 23 6 7 Timing Register A 6 25 6 8 Timing Register B 6 27 6 9 Global Timing Register 6 28 6 10 Refresh Timing Register 6 29 7 1 DECchip 21071 DA CSR Addresses 7 7 7 2 Diagnostic Control Status Register 7 10 7 3 PCI Error Address Register 7 14 7 4 System Bus Error Address Regist...

Page 18: ...r 9 32 9 19 Watchdog Timer TOY Clock Command Register 9 35 10 1 Formation of Address Modifier Codes from Scatter Gather Entry 10 6 10 2 VIC Block Transfer Control Register 10 8 10 3 VME Address 10 12 10 4 PCI Address 10 13 10 5 VME Interface Processor Page Monitor CSR 10 14 10 6 Interprocessor Communication Register Map Through VIF_ABR 10 15 10 7 Arbiter Requester Configuration Register 10 19 10 8...

Page 19: ...ell Operators 12 3 12 3 Digital Alpha VME 4 Console Command Summary 12 18 A 1 VMEbus J1 Connector A 2 A 2 Console J6 and Serial J7 Connector Pinouts A 3 A 3 Ethernet J9 Connector Pinouts A 4 A 4 Primary Breakout Module Connector Pinouts A 4 A 5 Keyboard and Mouse J1 Connector A 8 A 6 Parallel Port J6 Connector A 8 A 7 PMC I O Companion Card Mouse J2 Connector A 10 A 8 PMC I O Companion Card Keyboa...

Page 20: ......

Page 21: ...scriptions to program the module A secondary audience consists of manufacturing technicians who install the module and field technicians who diagnose problems and replace modules This manual does not explain how to use specific operating system programming interfaces For this information see the appropriate operating system documentation Structure of this Manual This manual consists of 13 chapters...

Page 22: ...isters Chapter 8 PCI bus describes the PCI bus the base of the I O subsystem The chapter describes the various I O devices and their registers Chapter 9 Nbus decribes the Digital Alpha VME 4 module s Nbus The discussion includes the Nbus address space and registers This chapter also includes information on ROM the Super I O chip the keyboard and mouse controller the time of year TOY clock interval...

Page 23: ...t not read Binary multiples The abbreviations K M and G kilo mega and giga represent binary multiples and have the following values K 210 1024 M 220 1 048 576 G 230 1 073 741 824 For example 2 KB 2 kilobytes 2 3210 bytes 4 MB 4 megabytes 4 3220 bytes 8 GB 8 gigabytes 8 3230 bytes Addresses Unless otherwise noted addresses and offsets are hexadecimal values Bit Notation Multiple bit fields can incl...

Page 24: ...dwords Hexword 16 32 256 2 Octawords Examples The prompts input and output in examples are shown in a monospaced font Interactive input is differentiated from prompts and system output with bold type For example echo This is a test This is a test Ellipsis points indicate that a portion of an example is omitted Keyboard Keys The following keyboard key conventions are used throughout this manual Con...

Page 25: ...xadecimal number For example 19 is decimal but 0x19 and 0x19A are hexadecimal see also Addresses Otherwise the base is indicated by a subscript for example 1002 is a binary number Ranges and Extents Ranges are specified by a pair of numbers separated by two periods and are inclusive For example a range of integers 0 4 includes the integers 0 1 2 3 and 4 Extents are specified by a pair of numbers i...

Page 26: ...er either privileged or unprivileged software can trigger UNPREDICTABLE results or occurrences UNPREDICTABLE results or occurrences do not disrupt the basic operation of the processor The processor continues to execute instructions in its normal manner In contrast UNDEFINED operations can halt the processor or cause it to lose information The terms UNPREDICTABLE and UNDEFINED can be further descri...

Page 27: ... halt or hang the system or any of its components For example a security hole would exist if some UNPREDICTABLE result depended on the value of a register in another process on the contents of processor temporary registers left behind by some previously running process or on a sequence of actions of different processes UNDEFINED Operations specified as UNDEFINED can vary from moment to moment impl...

Page 28: ...igital Equipment Corp Intel SIO82378 Chip Specification Intel Corp Internetworking with TCP IP Vol I Principles Protocols and Architecture Second edition Prentice Hall PCI Local Bus Specification Intel Corp NCR 53C810 Specification National Cash Register Co NCR 53C720 Programming Guide National Cash Register Co SIO Chip 82378ZB and 8259 Data Sheets Intel Corp VIC64 Specification Cypress Semiconduc...

Page 29: ... Component Interconnect PCI as the on board bus for the interconnection of high performance SCSI Ethernet and VME interfaces as well as the connection of industry standard PCI mezzanine cards PMCs IEEE P1386 1 standard The Digital Alpha VME 4 processors are supported by the VxWorks for Alpha and Digital UNIX operating systems 1 2 Functional Specifications Table 1 1 lists the Digital Alpha VME 4 pr...

Page 30: ...R 53C810 PCI based SCSI 2 processor single ended 8 bit with DMA up to 10 MB transfer rate with connection through the VMEbus P2 connector Serial and parallel interfaces Two asynchronous DEC423 ports 75 to 19200 baud through front panel MMJ connectors Keyboard and mouse support for graphics options on either the secondary breakout module or the PMC I O companion card Extended parallel port through ...

Page 31: ...d Mouse Controller Interval Timer TOY Clock Watchdog Timer NVRAM DS1386 Nbus 8 Bits PCI to PCI Bridge Ethernet Controller SCSI Controller PCI VME Bridge PCI Bus 32 Bits PCI PMC option 0 slot VME Connectors ML013270 Bcache 64 epiData 32 128 memdata PCI PMC option 1 slot PCI Host Bridge 21071 DA CPU Board PCI to Nbus Bridge I O Board PMC Expander Card Product Overview 1 3 ...

Page 32: ...pation for the Digital Alpha VME 4 module Stresses beyond those specified may cause permanent damage to the module Table 1 2 Physical and Environmental Specifications Characteristic Specification Industry standard VME 6U module Operating temperature 0 C to 40 C 32 F to 104 F Storage temperature 40 C to 66 C 40 F to 151 F Temperature change 20 C hour 36 F hour Relative humidity 5 to 95 noncondensin...

Page 33: ... max PMC Option Slot Budget 3 0 A max N A N A 15 W max Notes Power and heat dissipation assumes nominal voltages 5 0 V 12 0 V and 012 V Power numbers are based on actual measured data Add 10 to the current and power values for a worst case power and heat scenario SCSI Termination is enabled by default You can disable this option by resetting the jumper on the primary breakout module as explained i...

Page 34: ......

Page 35: ...actory return is necessary Caution You must install the primary breakout module 54 24663 01 included in your hardware kit see Figure 2 7 Applying power to the Digital Alpha VME 4 module WITHOUT that primary breakout module in place or WITH the breakout module included with the AXPvme 160 166 or 230 P N 54 22605 01 in place may damage your backplane the Digital Alpha VME 4 module or both Figure 2 1...

Page 36: ...pha VME 4 module Memory modules Cache memory modules Secondary breakout module Primary breakout module Table 2 1 lists Digital Alpha VME 4 hardware kit items The kits in Table 2 1 contain hardware only The option you receive may also include software licenses or software depending on what is ordered 2 2 Installation Procedures ...

Page 37: ...ha VME 4 module I O assembly 70 32976 02 includes 2 MB cache 54 24325 02 54 24319 01 Digital Alpha VME 4 Primary breakout module 1 54 24663 01 Digital Alpha VME 4 Secondary breakout module 54 24729 01 Alpha VME 4 228 and 4 288 Single Board Computers User Guide and Technical Description EK DAVME TD Antistatic wriststrap 12 36175 01 Optional PMC I O Companion Card PMC I O Companion Card 54 24665 01 ...

Page 38: ...ble is required and must be properly terminated The exact cable requirements depend upon the enclosure disk mounting and so forth A PC internal SCSI cable will work if you are connecting to an internal disk and the cable has a SCSI terminator or if the last disk or other SCSI device has an internal terminator You can use the Digital SCSI cables listed in Table 2 4 for this purpose To attach a prin...

Page 39: ...ection to external drives2 Digital 17 01244 01 02 03 SCSI 102 87 cm 40 5 in cable with six 50 pin female IDC connectors and an included 50 pin IDC SCSI terminator for connection to the Alpha VME breakout module and up to 4 internal drives with the terminator on the last connector Digital 17 03459 02 SCSI 220 98 cm 87 in cable with five 50 pin female IDC connectors for connection to the Alpha VME b...

Page 40: ... the circuits on the modules in your Digital Alpha VME 4 kit When you handle modules wear the antistatic wriststrap with the wire clipped to the frame of your VME chassis Also place the modules on top of the conductive plastic bags they came in while you work Note There must be sufficient space on the back of the VME backplane slot or slots selected to install the primary breakout module The Digit...

Page 41: ... 4 5 6 7 8 512 KB 2 MB C B A 9 Cache memory connectors Memory connectors Cache configuration select jumper J9 Power and VME slave activity watchdog timeout LEDs Status display Cache memory size and speed select jumper J10 I O module connector VME connectors SROM 8 pin Installation Procedures 2 7 ...

Page 42: ...l port Auxiliary serial port Reset halt switch Twisted pair Ethernet connector Connector to CPU module on back of I O module Debug jumper not installed for normal operation Configuration switchpack PMC I O companion card connector Ethernet Address ROM NVRAM TOY clock 2 8 Installation Procedures ...

Page 43: ...ttery will last for about 10 years with the Digital Alpha VME 4 module power turned off 2 Closed Enables writing of flash ROMs under program control Open Disables writing of flash ROMs 3 Closed Resets the Digital Alpha VME 4 module on VMEbus Reset signal Open Does not reset the Digital Alpha VME 4 module on VMEbus Reset signal 4 Closed Digital Alpha VME 4 module is VMEbus system controller Open Di...

Page 44: ... closed for reliable system operation during a VMEbus Reset 3 Install the memory module on your Digital Alpha VME 4 module Figure 2 4 in the following manner Populate bank 0 first then bank 1 if necessary Memory installed in a bank must be the same size and speed Align pin 1 of the memory module with pin 1 on the connector The position of the orientation notches see in Figure 2 4 assure proper con...

Page 45: ... the Main Memory Modules MLO 013246 3 1 2 4 Memory bank 0 slots A and B Memory bank 1 slots A and B Orientation notches Memory connector Table 2 8 shows all possible valid memory configurations Installation Procedures 2 11 ...

Page 46: ...16 16 64 16 16 16 16 64 32 32 96 16 16 32 32 96 32 32 16 16 128 32 32 32 32 4 Cache memory DIMMs are installed on your Digital Alpha VME 4 module by Digital Pin 1 of the DIMM is aligned with pin 1 on the cache connector The position of the orientation notch on the cache memory DIMM in Figure 2 5 see denotes the location of pin 1 2 12 Installation Procedures ...

Page 47: ...nd J10 jumpers are preconfigured for your Digital Alpha VME 4 module by Digital Table 2 9 Table 2 10 and Figure 2 2 show jumper settings and locations for informational purposes only Table 2 9 J9 Cache Jumper Settings Size A B C D 512 KB Out Out In In 2 MB Out Out In In Installation Procedures 2 13 ...

Page 48: ...Out Out Reserved Note If you are installing the PMC I O companion card proceed to Section 2 2 1 later in this chapter and complete the installation instructions before continuing on to step 6 6 Install the Digital Alpha VME 4 module into the VME chassis refer to Figure 2 6 Note that the module requires two adjacent backplane slots Secure the module with screws as shown in callout 2 14 Installation...

Page 49: ... see Figure 2 7 Applying power to the Digital Alpha VME 4 module WITHOUT that primary breakout module in place or WITH the breakout module included with the AXPvme 160 166 or 230 P N 54 22605 01 in place may damage your backplane the Digital Alpha VME 4 module or both Also do not press on the LED window when you install the module Installation Procedures 2 15 ...

Page 50: ... termination by placing the jumper across pins 3 and 5 8 Set the watchdog signal jumper on the breakout module refer to Figure 2 8 The Digital Alpha VME 4 module supplies an external watchdog reset signal that you can connect to a monitoring device If you make no connection to this external signal the setting of the jumper makes no difference Setting the jumper across pins 4 and 6 default provides...

Page 51: ...l is low during normal operation and high during a watchdog timer reset provided that pullup power is connected Figure 2 8 Primary Breakout Module Jumpers 5 3 1 6 4 2 SCSI Termination Enabled Watchdog Pullup 5 3 1 6 4 2 SCSI Termination Disabled Watchdog No Pullup MLO 013261 9 If your Digital Alpha VME 4 system has SCSI devices connect the SCSI cable to the primary breakout module refer to Figure ...

Page 52: ...t module refer to Figure 2 10 may damage your backplane the Digital Alpha VME 4 module or both Never insert a module other than an Digital Alpha VME 4 module into a slot opposite the breakout module The breakout module feeds power to several of the user defined pins on the P2 backplane connector This may damage another VME module It is recommended that the slot number and type of breakout module b...

Page 53: ...the hardware kit which you can connect to the primary breakout module If you use the secondary breakout module set the jumpers on that module as shown in Figure 2 11 Note An incremental clearance of at least 56 25 mm 2 25 inches is required to install the secondary breakout module Installation Procedures 2 19 ...

Page 54: ...oard Mouse Disabled 3 1 4 2 3 1 2 4 Mouse and keyboard connector Mouse and keyboard Y cable 17 04230 01 Keyboard and mouse jumper configurations Parallel port see Appendix A for pinouts 12 Connect the secondary breakout module to the primary breakout module as shown in Figure 2 12 2 20 Installation Procedures ...

Page 55: ...d pair Ethernet connector See Figure 2 13 Associated with the Ethernet connector are devices to convert from twisted pair to ThinWire P N DETTR AA See Table 2 4 14 Connect the console terminal cable to the Digital Alpha VME 4 module refer to Figure 2 13 15 If you have an auxiliary terminal connect it now Set your console terminal to a speed of 9600 bits second an 8 bit data word and no parity Inst...

Page 56: ...Figure 3 1 and the Digital Alpha VME 4 module runs its power up self test display POST This takes about 30 seconds The POST runs a number of tests that show their status on the LED display These tests complete successfully when the display counts down to zero The POST then runs a number of additional tests that display their status on the console terminal These tests have completed successfully wh...

Page 57: ...panion card with the Digital Alpha VME 4 you must have three adjacent slots available Figure 2 14 PMC I O Companion Card Layout MLO 013366 7 9 1 3 4 5 8 2 6 5 0 V 3 3 V 10 I O module connector on back of PMC I O companion card PCI to PCI bridge chip Power LED Keyboard connector Mouse connector Debug socket Installation Procedures 2 23 ...

Page 58: ...om the I O module and slide the connecting edges together until the connector on the bottom of the PMC I O companion card is aligned with its mating connector on the top side of the I O module as shown in Figure 2 15 Caution You must align the connector precisely If the alignment is not precise the force required for normal connector mating is sufficient to damage the connector housing and pins 5 ...

Page 59: ...perly The press fit shoulder washer that holds the screw washer in place might become disengaged if you apply excessive pressure to the front panel 7 Tighten the six screws on the handles as shown in Figure 2 16 8 If being used connect the mouse and keyboard cables at the locations shown in Figure 2 14 Installation Procedures 2 25 ...

Page 60: ...Figure 2 15 Connecting the PMC I O Companion Card MLO 013265 2 26 Installation Procedures ...

Page 61: ...e power or toggle the Reset switch the Digital Alpha VME 4 module runs its POST The module runs a series of tests stored in the serial read only memory SROM and then runs a series of console code tests stored in the flash ROMs The SROM tests display their test number on the LED display during execution If an SROM test fails the LED display flashes the failing test number Refer to Table 2 11 for a ...

Page 62: ...e starts at 0X8000 1 1 The debug jumper is about to be checked If the jumper is IN then the initialization process traps to the minidebugger 0 0 Written by the PAL reset entry point This indicates that the firmware has been decompressed and is starting Note Use of a graphic mode console option may preclude the display of initial POSTs See the documentation supplied with your graphics option for de...

Page 63: ...nostics are always executed on power up and use decreasing numeric codes 8 7 1 to indicate status on the dot matrix display All SROM based tests must pass successfully before the flash ROM based diagnostics and console diagnostics are run If one or more SROM diagnostics fail the flash ROM based diagnostics and the console diagnostics will not be loaded and a single prompt will be displayed on the ...

Page 64: ...nd you are experiencing diagnostic failures remove it and repeat the POST It is important to remember that the dot matrix display is useable by operating system software and by user applications as well Once the system is booted the dot matrix display is no longer under control of the console code and may change The console will automatically clear the display before booting any image Table 2 13 l...

Page 65: ...k that the TOY NVRAM device is seated properly see Figure 2 3 Green LED on dot matrix displays a flashing letter F on power up Check the seating of the Network Address ROM see Figure 2 3 Green LED on dot matrix displays a flashing letter G on power up Check the seating of the twisted pair cable and the nearest network transceiver Green LED on dot matrix displays a flashing letter I on power up Che...

Page 66: ...4 ZE Alpha VME 4 288 UNIX Runtime EBV14 RE Alpha VME 4 288 VxWorks Runtime EBV14 XE 16 MB Memory DIMM 80 bits 70 ns EBMXM DB 32 MB Memory DIMM 80 bits 70 ns EBMXM EB 64 MB Memory DIMM 80 bits 70 ns EBMXM FB PMC I O Companion Card EBV1P AA 2 5 2 Hardware Warranty Your Digital Alpha VME 4 system comes with a limited warranty consisting of Return to Digital hardware support The warranty provides free...

Page 67: ...ment part at full country list price 2 5 2 4 Eligible Parts Field replaceable units as defined by Digital are the only parts eligible for coverage Field replaceable units in need of repair due to improper treatment or use are not eligible for return Improper treatment includes but is not limited to lifted or burnt etches or delamination due to non Digital repair or modification If you return a fie...

Page 68: ...Maintenance Digital software products are warranted to conform to the applicable Software Product Description This means that Digital will remedy any conformance that you report during the warranty period Warranty of third party software products sold by Digital is as designated in the Software Product Description The term of the warranty and the manner in which Digital will remedy any non conform...

Page 69: ...Secondary Breakout Module 54 24663 01 VME Primary Breakout Module EBV14 E 70 32976 02 288 MHz Single Board Computer 2 board set 2 MB cache 54 24729 01 VME Secondary Breakout Module 54 24663 01 VME Primary Breakout Module EBV1P AA 54 24665 01 PMC I O Companion Card 17 04230 01 Cable Y Adapter IBM ThinkPAD EBMXM DB 54 24659 AB 16 MB 2x8 DIMM Set EBMXM EB 54 24659 AA 32 MB 2x16 DIMM Set EBMXM FB 54 2...

Page 70: ......

Page 71: ...Alpha VME 4 Computer 3 1 Controls and Indicators Figure 3 1 shows the front panel controls and indicators of the Digital Alpha VME 4 module and Table 3 1 describes their function Operating the Digital Alpha VME 4 Computer 3 1 ...

Page 72: ... under the software control of the operating system or an application program VME Slave Activity Watchdog Timeout LED An amber LED with two functions The LED flashes when the Digital Alpha VME 4 module is accessed as a slave by another device on the VMEbus The LED lights continuously when the watchdog timer has timed out Note The LED can appear to light continuously when the module is receiving sl...

Page 73: ...d Caution Depending on the operating system and applications running at the time this could damage application files You use the operating system command to enter console mode The operating system executes a HALT instruction The operating system encounters a fatal error 3 2 2 Exiting Console Mode You can exit console mode by issuing the boot start or continue command For more information use the h...

Page 74: ...pecified with the boot command BOOTDEF_DEV Specifies the device list from which bootstrapping is to be attempted when no path is specified with the boot command BOOTED_DEV Specifies devices to be used by the last or currently in progress bootstrap attempt BOOTED_FILE Specifies the file name to be used by the last or currently in progress bootstrap attempt BOOTED_OSFLAGS Specifies arguments to be p...

Page 75: ...ted during bootstrap EWA0_ARP_TRIES Specifies the number of transmissions to be attempted before the Internet Address Resolution Protocol ARP fails EWA0_BOOTP_FILE Specifies a generic file name to be included in an Internet Boot Protocol BOOTP request EWA0_BOOTP_ SERVER Specifies a server name to be included in a BOOTP request EWA0_BOOTP_TRIES Specifies the number of transmissions that are to be a...

Page 76: ...ngs include TWISTED PAIR and FULL full duplex twisted pair EWA0_PROTOCOLS Specifies the network protocol to be enabled for booting and other functions EWA0_TFTP_TRIES Specifies the number of transmissions that are to be attempted before the Trivial File Transfer Protocol TFTP fails LANGUAGE Specifies the current console terminal language integer ID LANGUAGE_NAME Specifies the current console termi...

Page 77: ...the Digital UNIX operating system or VxWorks for Alpha kernel see the operating system documentation If you are booting the Digital UNIX operating sytem see the Digital UNIX Installation Guide If you are booting the VxWorks for Alpha kernel see the VxWorks Digital Alpha VME Single Board Computers Hardware Supplement and the VxWorks Programmer s Guide 3 5 Updating Firmware For information on updati...

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Page 79: ...and or system reset By an operator at the console prompt 4 2 1 POST Diagnostics The diagnostic reset environment is entered as a result of power being applied to the system or reset being applied to a previously running system In this mode a sequence of RBDs is executed without user intervention Once the SROM code has been loaded into the 8 KB internal instruction cache a very basic system initial...

Page 80: ... test and the sequence attempts to continue to console mode An attempt is also made to write the diagnostic log to the console terminal You can affect the POST sequence by using certain user selectable control parameters implemented as environment variables that allow the initialization to continue despite the existence of some errors that you may not wish to treat as fatal 4 2 2 Console Prompt Di...

Page 81: ... t 1 DECchip 21040 network interface CSR test nicsr_diag t 2 DECchip 21040 network interface CSR test nicsr_diag t 3 NVRAM TOY Clock NVRAM test ds1386_diag t 1 NVRAM test ds1386_diag t 2 NVRAM test ds1386_diag t 3 Time of year TOY clock register test ds1386_diag t 4 TOY clock register test ds1386_diag t 5 SCSI SCSI device test ncr810 t 1 SCSI device test ncr810 t 2 SCSI device test ncr810 t 3 SCSI...

Page 82: ...e 4 1 VMEbus Interface Tests VIP PCI configuration register test vip_diag t 1 VIP register write read test vip_diag t 2 VIC register write read test vip_diag t 3 Scatter gather RAM test vip_diag t 4 MISC Ethernet hardware address test enet_diag t 1 Ethernet hardware address test enet_diag t 2 4 3 2 SROM Initialization Countdown During SROM initialization the LED ASCII display executes a countdown ...

Page 83: ... scrubbed 4 4 Bcache has been initialized and enabled 3 3 Bcache and main memory have been scrubbed to valid error checking correction ECC 2 2 Firmware image has been loaded from the flash ROM Image starts at 0x8000 1 1 Debug jumper is about to be checked If jumper is IN then trap to the mini debugger 0 0 Written by the console firmware in PAL reset entry point Indicates that the firmware has been...

Page 84: ...st through power cycles and a write read compare of specific NVRAM locations used for diagnostics It also checks for uninitialized NVRAM by comparing the stored checksum with the calculated checksum Description This test executes at the beginning of console boot before the console drivers and devices have been initialized Test Name None executes on power on 4 6 Diagnostics ...

Page 85: ...inning of console boot before the console drivers and devices have been initialized This test provides the following coverage Memory bits Stuck bits bit transition fault or bit coupling fault Decoder logic An address selects no memory two or more addresses select the same memory cell or one address selects more than one cell Sense amplifier logic Stuck fault or coupling fault Component and path co...

Page 86: ...onsole Diagnostic Test Descriptions This section provides details on the tests which are available to the console that you might run during system initialization testing or run from the console 4 8 Diagnostics ...

Page 87: ...ecks the following logic Heartbeat timer and interrupt delivery mechanism Module clear heartbeat register Heartbeat Timer Test Console Command hbeat_diag t 1 Command Option dd print detailed test information on each pass Miscellaneous Notes This is a POST diagnostic The test expects timer interrupts to be enabled If they are not enabled an interrupt count of zero results You cannot run this test c...

Page 88: ...upt on terminal count After the timer is initially programmed to mode 0 and loaded with a count value the OUT output is low and remains low until the internal count value reaches zero When the count value reaches zero OUT output is asserted high and remains high until timer 2 is reprogrammed The event of OUT transitioning from low to high should generate a CPU interrupt The interrupt service routi...

Page 89: ... the interrupt count is within a certain range based on the count value the timer was programmed with and the duration of time that interrupts were enabled Console Command i8254_diag t 2 Miscellaneous Notes The interrupt enable bits for timers 0 and 2 bits 4 and 5 of the interrupt status register at address 0x4010 are not directly writable Bit 4 is toggled by writing to address 0x4010 bit 5 is tog...

Page 90: ...hat timer 0 counts down Timer 0 is the only interrupt that is enabled during this test The event of OUT transitioning from low to high should generate a CPU interrupt The ISR invoked due to the timer generated interrupt increments an interrupt counter and sets a global flag indicating the interrupt took place and that software was dispatched to the correct point The test verifies that the interrup...

Page 91: ... 2 is programmed to mode 0 interrupt on terminal count After the timer is initially programmed to mode 0 and loaded with a count value the OUT output is low and remains low until the internal count value reaches zero When the count value reaches zero OUT output is asserted high and remains high until timer 2 is reprogrammed The event of OUT transitioning from low to high should set the timer 2 sta...

Page 92: ...imer Timer 1 is programmed to mode 3 square wave mode After the timer is initially programmed to mode 3 and loaded with a count value the OUT output is low and remains low until the internal count value reaches zero When the count value reaches zero OUT output is asserted high and remains high until timer 1 is reprogrammed A global interrupt count flag is checked verifying whether the interrupt se...

Page 93: ...C13 row C B A 14 13 12 11 Configuration for Interval Timer test 4 MASTER SLAVE Alpha VME For test 4 the MASTER signals must be the input for the second Alpha VME module Connect pins C11 and C14 of the MASTER to C14 of the SLAVE With a second jumper connect C12 and C13 of the MASTER to C13 of the SLAVE VMEbus P2 Connector row C B A 14 13 VMEbus P2 Connector SLAVE C B A 14 13 12 11 VMEbus P2 Connect...

Page 94: ... on the network medium twisted pair cable It concurrently listens to the line which carries its own transmissions and returns them to the receive ring in main memory Received packets not identified as test packets are discarded for the duration of the test Note To run the external loopback test you must use a 10baseT loopback connector H4082 AA The external loopback test does not run if the device...

Page 95: ...Cchip 21040 and prints them to the standard output Console Command nicsr_diag t 2 DECchip 21040 Configuration Register Test This test performs writes and reads to the chip s configuration registers with data patterns of all 1s all 0s and alternating 1s and 0s Upon exiting the test returns the configuration registers to their initial values Console Command nicsr_diag t 3 Command Option dd print det...

Page 96: ...contains 128 pages However the first page has reserved addresses for the realtime clock registers NVRAM March I Test This test writes reads and compares all 32 KB of NVRAM with data patterns of all 1s all 0s alternating 1s and 0s and shifting 1s and 0s If the quick verify option is set default only the first location of each page is tested The no quick verify option tests every location 32 KB of t...

Page 97: ...letion If the module is reset during this test the NVRAM contents are undefined Console Command ds1386_diag t 2 Command Options dd print detailed test information on each pass nqv test every location in NVRAM default is to test 1 location per 256 byte page Miscellaneous Note This diagnostic is an extended test NVRAM March II Test This test verifies NVRAM addressing by marching write read and compa...

Page 98: ...d and the transfer enable bit is set to 0 to disable updates to the registers while the diagnostic is in progress The diagnostic bit patterns are then walked through all 14 registers Next the seconds minutes hours day month and year registers are programmed such that the next clock tick rolls over for each of these parameters The updates to the registers are started and updated for a three second ...

Page 99: ...ds the current value of the seconds register Then the test sleeps for 1 2 seconds and reads the seconds register again expecting it to have incremented with the exception of the rollover case The rollover case is where the seconds register advanced from 59 to 0 If the rollover case is encountered the test sleeps for another second and reads the register again This is repeated four times Console Co...

Page 100: ...dress ROM to screen np no print if specified LAN address ROM is not printed to screen Miscellaneous Notes The LAN address ROM octets must be read by using longword aligned byte accesses This diagnostic is an extended test LAN Address ROM Verification Test This test verifies the format of the data in the LAN address ROM It verifies that the octets are ordered appropriately and that the checksums ar...

Page 101: ...hecksum Octet 2 Checksum Octet 1 Address Octet 5 Address Octet 4 Address Octet 3 Address Octet 2 Address Octet 1 Address Octet 0 Address Octet 0 Address Octet 1 Address Octet 2 Address Octet 3 Address Octet 4 Address Octet 5 Checksum Octet 1 Checksum Octet 2 Test Pattern FF Test Pattern 00 Test Pattern 55 Test Pattern AA Test Pattern FF Test Pattern 00 Test Pattern 55 Test Pattern AA Diagnostics 4...

Page 102: ...e tests fail the console SCSI driver does not restart after the test This causes SCSI devices connected to the system to be removed from the device list and any attempts to run the disk exerciser or boot from a disk fails The command show device lists the currently installed devices NCR810 PCI Configuration Register Test This test prints the current setting of the NCR810 PCI configuration register...

Page 103: ...lternating 1s and 0s The test also verifies parity checking and that the SCSI reset control lines can be toggled internally Console Command ncr810_diag t 5 NCR810 Internal Live Bus Loopback Test This test performs an internal SCSI loopback that also drives the signal lines on the SCSI bus All devices must be removed from the SCSI bus before running this test Devices on the bus interfere with the t...

Page 104: ...terrupt that is dispatched to the CPU through the SIO controller The console PALcode dispatches to the NCR810_diag ISR which clears the interrupt Console Command ncr810_diag t 7 Miscellaneous Notes These tests do not run in parallel with the SCSI exerciser tests No external loopback connectors are needed for the loopback tests References NCR 53C810 PCI SCSI I O Processor specification Revision 2 1...

Page 105: ...o the user is asked to verify the watchdog LED is now on At the end of the test the watchdog timer and diagnostic in progress bit are disabled Console Command wdog_diag t 1 Command Options dd print detailed test information on each pass nc no confirmation user is not prompted to verify state of LED np no print overrides the nc option no user prompts Miscellaneous Note The purpose of setting the di...

Page 106: ...and base address 0 1 2 and 3 are compared to an expected value The remaining longwords are always read and displayed only if the dd option is present Console Command vip_diag t 1 Command Option dd print detailed test information VIP Register Write Read Test This test ensures that the bits of a VIP register can be written and read correctly verifying the data path and internal access Console Comman...

Page 107: ...s test verifies the integrity of the scatter gather RAM by performing write read and verify of various patterns to the entire scatter gather RAM Console Command vip_diag t 4 Command Option dd print detailed test information on each pass Diagnostics 4 29 ...

Page 108: ...ort initialization Bcache configuration Main memory configuration Bcache initialization B 8 7 6 5 4 3 2 1 LED Display Power on Reset Notes Serial ROM Serial ROM Serial ROM Serial ROM Serial ROM Serial ROM Serial ROM ML013408 Check debug jumper jump to SROM mini debugger if jumper installed else start the console firmware Bcache and main memory scrubbed to valid ECC Firmware loaded from flash ROM t...

Page 109: ...st Console test Console test Console test Console test Console test Console test ML013409 SCSI Test Heartbeat Test Interval Timer Tests A B C D E F G Time of Year Tests Serial Com Port Tests Ethernet ROM Tests Ethernet Internal Loopback Tests C Diagnostics 4 31 ...

Page 110: ...Figure 4 5 Console POST Flows Watchdog Test C LED Display Notes Console test Console test Console test ML013410 VIP VIC Tests Console Prompt H I 4 32 Diagnostics ...

Page 111: ...e Local I O space for registers residing on the system bus that is registers in the 21071 CA and 21071 DA chips PCI space Note The system bus represents the 21064A pin bus as well as control signals between the 21071 CA and 21071 DA chips The PCI defines three physical address spaces PCI memory space for memory residing on the PCI PCI I O space PCI configuration space In addition to these address ...

Page 112: ... PCI Sparse Memory PCI Dense Memory 2 0000 0000 2 FFFF FFFF 3 0000 0000 3 FFFF FFFF General Use VIP VME Window PCI System Direct Mapped Other Map I O Programmed by Firmware 2 GB 1 8000 0000 1 9FFF FFFF 21071 CA CSR 21071 DA CSR 1 A000 0000 1 AFFF FFFF 0 0000 0000 0 FFFF FFFF Cacheable Memory Space Noncacheable Memory 1 0000 0000 1 7FFF FFFF Programmed by Firmware 2 GB Programmed by Firmware 384 MB...

Page 113: ...nds to all addresses in this space Dstream access only 01 1011 PCI interrupt acknowledge or PCI special cycle The 21071 CA expects the 21071 DA to respond to all addresses in this space A read transaction causes a PCI interrupt acknowledge a write transaction causes a special cycle Dstream access only 01 110x I O space 16 MB of PCI space The lower 256 KB of this space must be used for addressing t...

Page 114: ...ata buffers Dstream access only 5 1 1 Cacheable Memory Space 0x000000000 to 0x0FFFFFFFF The 21071 CA recognizes the 4 GB of quadrant 0 corresponding to sysBus 33 32 00 as cacheable memory space The 21071 CA responds to all read and write accesses in this space Some or all of main memory can be programmed to be in cacheable space 5 1 2 Noncacheable Memory Space 0x100000000 to 0x17FFFFFFF The 21071 ...

Page 115: ...causes a PCI I O read or PCI I O write command respectively Bits sysBus 33 29 identify the various address spaces on the system bus Bits sysBus 6 3 generate the length of the PCI transaction in bytes the byte enables and ad 2 0 on the PCI bus see Table 5 2 Bits sysBus 28 8 correspond to the quadword PCI addresses and are sent out on ad 23 3 during the address phase on the PCI Bits ad 31 24 are obt...

Page 116: ... 0 0 0 0 0 0 0 0 0 0 LJ03953A AI Length in Bytes sysBus Address sysBus Address PCI I O Address PCI Memory Space Byte Offset 33 29 28 23 22 08 07 05 04 03 02 00 1 0 1 1 0 33 29 28 23 22 08 07 05 04 03 02 00 31 HAXR0 Address Translation for Lower 256K Bytes of PCI I O Space Address Translation for Remaining 64M bytes 64K Bytes of PCI Memory Space 24 23 03 02 00 31 24 23 00 31 24 23 03 02 00 Length i...

Page 117: ... 0001 CPU address 7 01 10 10 Illegal2 11 10 Illegal2 Longword 00 11 0000 CPU address 7 00 Longword 01 11 Illegal2 Longword 10 11 Illegal2 Quadword 11 11 0000 000 1 Byte enable set to 0 indicates that byte lane carries meaningful data 2 These combinations are architecturally illegal If there is an access with this combination of address 6 3 the 21071 DA responds to the transactions but the results ...

Page 118: ...various fields of PCI ad 31 0 during the address phase of a configuration read or write cycle Table 5 3 PCI Configuration Space Definition Target Bus ad Bits Definition Primary PCI Bus 31 11 Decoded from sysAdr 20 16 according to Table 5 4 Can be used for IDSEL or don t care states Typically the IDSEL pin of each device is connected to a unique ad line 10 8 Function select 1 of 8 from sysAdr 15 13...

Page 119: ... 0000 0010 0000 0000 0000 0 01111 0000 0100 0000 0000 0000 0 10000 0000 1000 0000 0000 0000 0 10001 0001 0000 0000 0000 0000 0 10010 0010 0000 0000 0000 0000 0 10011 0100 0000 0000 0000 0000 0 10100 1000 0000 0000 0000 0000 0 10101 to 11111 0000 0000 0000 0000 0000 0 5 1 7 1 PCI Configuration Cycles to Primary Bus Targets Primary PCI bus devices are selected during a PCI configuration cycle if The...

Page 120: ... as listed here Bits Taken From Operation ad 23 16 sysAdr 28 21 Select a unique bus number ad 15 11 sysAdr 20 16 Select a device on the PCI typically decoded by the target bridge to generate IDSEL signals ad 10 8 sysAdr 15 13 Select one of eight functional units per device ad 7 2 sysAdr 12 7 Select a longword in the device s configura tion register space Each PCI to PCI bridge device can be config...

Page 121: ...espond to the quadword PCI addresses and are sent out on ad 26 3 during the address phase on the PCI Bits ad 31 27 are obtained from one of two host address extension registers HAXR0 and HAXR1 HAXR0 which is hardcoded as 0 is used for system bus addresses 0x200000000 to 0x21FFFFFFF that is when bits sysBus 31 29 are 0 The HAXR1 register maps system bus addresses 0x220000000 to 0x2FFFFFFFF that is ...

Page 122: ...s Translation for Remaining 112M Bytes of PCI Memory Space 27 26 03 02 00 01 0 0 01 31 27 26 00 31 27 26 03 02 00 Byte Offset Byte Offset Length in Bytes Longword Address HAXR1 Table 5 5 shows the generation of the byte enables and PCI address ad 2 0 from bits sysBus 6 3 Bits sysBus 33 5 are directly available from the CPU Bits sysBus 4 3 are derived from the longword masks cpucwmask 7 0 On read t...

Page 123: ...rchitecturally illegal If there is an access with this combination of address 6 3 the 21071 DA will respond to the transactions but the results are UNPREDICTABLE On write transactions the relationship between cpucwmask 7 0 and sysBus 4 3 is as follows If cpucwmask 1 0 is nonzero sysBus 4 3 is 00 If cpucwmask 3 2 is nonzero sysBus 4 3 is 01 If cpucwmask 5 4 is nonzero sysBus 4 3 is 10 If cpucwmask ...

Page 124: ...to one mapping between CPU addresses and PCI addresses A longword address from the CPU maps to a longword on the PCI thus the name dense space as opposed to PCI sparse memory space Byte or word accesses are not allowed in this space Minimum access granularity is a longword The maximum transfer length implemented by the 21072 chipset is a cache line 32 bytes on write transactions and a quadword on ...

Page 125: ...I to Physical Memory Addressing Incoming 32 bit memory addresses are mapped to the 34 bit physical memory addresses The 21071 DA allows two regions in PCI memory space to be mapped to system memory with two programmable address windows The mapping from the PCI address to the physical address can be direct physical mapping with an extension register or scatter gather mapped virtual These two addres...

Page 126: ...en the WENB bit in the other PCI base register must be cleared otherwise the two windows will overlap Based on the value of the PCI mask register the unmasked bits of the incoming PCI address are compared with the corresponding bit of each window s PCI base register If the base registers and the incoming PCI address match the incoming PCI address has hit that target window otherwise it missed that...

Page 127: ... SGEN bit of the PCI base register of the associated window If SGEN is cleared the DMA address is direct mapped The translated address is generated by concatenating bits from the matching window translated base register with bits from the incoming PCI address The PCI mask register determines which bits of the translated base register and PCI address are used to generate the translated address as s...

Page 128: ...tem memory The table is referred to as a scatter gather map The translated base register specifies the starting address of the scatter gather map Bits of the incoming PCI address are used as an offset from the base of the map The map entry provides the physical address of the page Each scatter gather map entry maps an 8 KB page of PCI address space into an 8 KB page of processor address space Each...

Page 129: ... of the scatter gather map table is determined by the size of the PCI target window as defined by the PCI mask register see Table 5 8 Because the scatter gather map is located in system memory bit sysBus 33 is always zero Bits sysBus 32 2 are obtained from the translated base register and the PCI address System Address Mapping 5 19 ...

Page 130: ...CI ad 30 13 1111 1111 1111 4 MB T_BASE 32 22 PCI ad 31 13 Figure 5 6 shows the entire translation process from the PCI address to the physical address on a window implementing scatter gather mapping The following list describes the translation operation 1 Bits ad 12 5 of the PCI address directly generate the page offset 2 The relevant bits of the PCI address as specified by the window mask registe...

Page 131: ... 07 10 11 0000 T_Base Compare sysBus Base Address Translated Base Register 33 03 10 11 n n n n Scatter Gather Map Address Driven on sysBus 33 13 12 32 05 Offset sysBus Page Number Physical Memory Location Driven on sysBus 20 01 Scatter Gather Entry Scatter Gather Map in Main Memory 6 Bit 0 is the valid bit for the page table entry System Address Mapping 5 21 ...

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Page 133: ... Subsystem Main Memory Data Path 4 chips Cache and Memory Controller CPU System Bus sysBus ML013274 Bcache The components of the cache and memory subsystem are distributed between the DECchip 21071 CA and the DECchip 21071 BA Together the chips are the interface between the system bus main memory and the Bcache see Figure 6 2 Cache and Memory Subsystem 6 1 ...

Page 134: ...ta Path Bit Assignments memData Lines sysData Lines memData 31 0 21071 BA0 31 0 memData 63 32 21071 BA1 63 32 memData 95 64 21071 BA2 95 64 memData 127 96 21071 BA3 127 96 sysData 15 0 The DECchip 21071 CA provides Bcache and memory control functions and also controls the data paths located in the 21071 BA chips The DECchip 21071 CA arbitrates between the CPU and the PCI host bridge when they requ...

Page 135: ... b 3 0 _we_l 4 b0 3 0 _adr 11 0 48 Row Col The following list summarizes the functions of the DECchip 21071 CA Arbitrates between the CPU and the 21071 DA for control of the system bus Controls filling the Bcache and extracting victims on CPU initiated transactions Controls probing the Bcache on direct memory access DMA transactions and invalidating the Bcache on DMA write hits Controls the loadin...

Page 136: ...The system bus controller consists of A sequencer that receives CPU and DMA command fields for decode Results from the system bus arbiter logic Status from the memory controller logic The sequencer then supplies machine state signals that are used to Generate requests for Bcache control and read to the memory controller Load data from the system bus into the read merge and write buffers Acknowledg...

Page 137: ...DA FCT162244ET AlphaPC64 10 The Bcache controller provides control for the secondary cache on CPU initiated memory read and write transactions that miss and on all CPU initiated memory LDx_L and STx_C transactions hits and misses On DMA initiated transactions the Bcache controller probes the cache and extracts or invalidates the cache line The 21071 CA supports a write back cache 6 3 Memory Contro...

Page 138: ...80 16 MB and 4 MB x 80 32 MB This provides for 16 32 48 64 80 96 or 128 MB of total system memory Figure 6 5 shows the maximum and minimum DIMM bank layouts Figure 6 5 Maximum and Minimum DIMM Bank Layouts Bank 1 DRAM 0 32 MB DIMM memdata 0 63 ECC Bank 0 DRAM 0 32 MB DIMM memdata 0 63 ECC Bank 1 DRAM 1 32 MB DIMM memdata 64 127 ECC Bank 0 DRAM 1 32 MB DIMM memdata 64 127 ECC Maximum 128 MB DRAM La...

Page 139: ...ions queued in the write buffer 6 3 5 Transaction Scheduler The memory interface does memory refresh cache line read and write transactions The memory controller has a scheduler that prioritizes all transactions and selects one to be serviced If the selected transaction is waiting for row address strobe RAS precharge and another higher priority transaction is initiated the scheduler deselects the ...

Page 140: ...r on a transaction while the error address and status are locked the following occurs The transaction is acknowledged with a hard error condition on the cack 2 0 or iocack 1 0 fields The LOSTERR bit in the error and diagnostics status register is set The lost error address and status are not recorded The hard error condition overrides STx_C transaction fail The lock bit is UNPREDICTABLE after LDx_...

Page 141: ...000 0220 Refresh timing register 1 8000 0240 Video frame pointer register 1 8000 0260 Presence detect low data register 1 8000 0280 Presence detect high data register 1 8000 0800 Bank 0 base address register 1 8000 0820 Bank 1 base address register 1 8000 0840 Bank 2 base address register 1 8000 0860 Bank 3 base address register 1 8000 0880 Bank 4 base address register 1 8000 08A0 Bank 5 base addr...

Page 142: ...ing register A 1 8000 0C40 Bank 2 timing register A 1 8000 0C60 Bank 3 timing register A 1 8000 0C80 Bank 4 timing register A 1 8000 0CA0 Bank 5 timing register A 1 8000 0CC0 Bank 6 timing register A 1 8000 0CE0 Bank 7 timing register A 1 8000 0D00 Bank 8 timing register A 1 8000 0E00 Bank 0 timing register B 1 8000 0E20 Bank 1 timing register B 1 8000 0E40 Bank 2 timing register B 1 8000 0E60 Ban...

Page 143: ... and system bus controllers The register is shown in Figure 6 6 and is defined in Table 6 2 Figure 6 6 General Control Register 0x180000000 15 MBZ 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LJ 04178 AI MBZ BC_BADAP BC_FRCP BC_FRCV BC_FRCD BC_FRCTAG BC_IGNTAG BC_LONGWR BC_NOALLOC BC_EN WIDEMEM MBZ SYSARB MBZ Cache and Memory Subsystem 6 11 ...

Page 144: ... the line is invalidated assuming BC_FRCV is reset the data is loaded into the cache and is returned to the CPU as cacheable Used for diagnostic testing of the cache RAM and for flushing the cache clearing BC_FRCV and cycling through the address range in the cache 8 BC_IGNTAG RW 0 Bcache ignore tag When set the probes of the Bcache act as if the valid bit was invalid All tag results are ignored an...

Page 145: ...ing 0X CPU priority 10 DMA priority 11 DMA strong priority 0 Reserved MBZ 6 6 2 Error and Diagnostic Status Register The error and diagnostic register contains read only status information for diagnostics and error analysis The register is shown in Figure 6 7 and is defined in Table 6 3 When an error occurs it sets one or more error bits BC_TAPERR BC_TCPERR NXMERR and locks the address of the erro...

Page 146: ...egister Field Name Type Description 15 WRPEND RO O Write pending When set indicates that valid write data is stored in the write buffer 14 LDXLLOCK LDx_L locked When set indicates that the lock bit for LDx_L is set and that the next STx_C may succeed Writing to any CSR or I O space location clears this lock bit 13 PASS 2 RO Chip version reads low on pass 1 and high on pass 2 12 9 Reserved MBZ cont...

Page 147: ...nsaction caused a BC_TAPERR BC_TCPERR or NXMERR error Locked with the error address Valid only when an error is indicated on BC_ TAPERR BC_TCPERR or MEMERR 3 NXMERR RW1C 0 Nonexistent memory error When set indicates that a read or write transaction occurred for an address that does not map to any memory bank CSR or I O quadrant Set only when address is unlocked 2 BC_TCPERR RW1C 0 Bcache tag contro...

Page 148: ...GEN 31 17 MBZ The upper bits of TAGEN 31 17 are not required to be set Therefore an implementation that does not allow the full 4 GB cacheable memory to be installed has the option to mask the upper bits of TAGEN 31 17 and so is not required to store a bit of the tag address in the tag address RAM To construct TAGEN 31 17 refer to Tables 6 4 and 6 5 The value shown in Table 6 4 based on the cache ...

Page 149: ...6 MB 1111 1000 0000 0000 31 27 128 MB 1111 1100 0000 0000 31 26 64 MB 1111 1110 0000 0000 31 25 32 MB 1111 1111 0000 0000 31 24 16 MB 1111 1111 1000 0000 31 23 8 MB 1111 1111 1100 0000 31 22 4 MB 1111 1111 1110 0000 31 21 2 MB 1111 1111 1111 0000 31 20 1 MB 1111 1111 1111 1000 31 19 512 KB 1111 1111 1111 1100 31 18 256 KB 1111 1111 1111 1110 31 17 128 KB 1 TAGEN 0 is reserved and must be zero Cach...

Page 150: ...000 0110 18 17 512 KB 0000 0000 0000 0010 17 256 KB 0000 0000 0000 0000 None 128 KB 1 TAGEN 0 is reserved and must be zero 6 6 4 Error Low Address Register When an error sets the BC_TAPERR BC_TCPERR or NXMERR bit in the error and diagnostic status register the error low address register latches the low order bits of the sysadr 20 5 address that caused the error If a victim read caused the error th...

Page 151: ...the address of the transaction is latched The register is shown in Figure 6 10 Bits 12 0 represent sysadr 33 21 Bits 15 13 are reserved and must be zero This register is read only It is not initialized and is only valid when an error is indicated Figure 6 10 Error High Address Register 0x1800000A0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LJ 04182 AI MBZ ERR_HADR 33 21 6 6 6 LDx_L Low Addres...

Page 152: ...I MBZ LDXL_HARD 33 21 6 6 8 Memory Control Registers The registers described in this section control memory configuration and timing Each bank of memory has one configuration register one base register and two timing registers The global timing register and refresh timing register apply to all banks 6 6 8 1 Presence Detect Low Data Register After a reset operation presence detect data is shifted f...

Page 153: ...set the data becomes valid after 148 system clock cycles Figure 6 14 Presence Detect High Data Register 0x180000260 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LJ 04187 AI PRES_DET 31 16 6 6 8 3 Base Address Registers Each memory bank set has a base address register as shown in Figure 6 15 The bits in the base address register are compared with the incoming address sysadr 33 23 to determine wh...

Page 154: ... 6 8 4 Configuration Registers Each memory bank set has a configuration register that contains mode bits memory address generation bits and bank decoding bits The configuration registers for banks 0 and 1 have the same format and the same limits for size and type of DRAMs used The registers are shown in Figure 6 16 and are defined in Table 6 6 Figure 6 16 Configuration Registers for Bank Set 0 0x1...

Page 155: ...to generate row or column addresses Memory interface width is set at 128 bits The field codes for S0_COLSEL 2 0 are S0_COLSEL 2 0 Row Column Bits 000 12 12 001 12 10 or 11 11 010 Reserved 011 10 10 1XX Reserved 5 S0_SUBENA RW 0 Enables subbanks defined by S0_SIZE When clear subbanks are disabled and the 3 0 _rasb0_l pins are asserted only during refreshes 1 Field names are for Bank 0 continued on ...

Page 156: ...iguration parameters for the bank are valid and access to the bank is allowed 1 Field names are for Bank 0 6 6 8 5 Bank Set Timing Registers Each bank has two timing registers A and B These registers contain the parameters for performing memory read and write transactions The format of the timing registers is identical for all banks A reset operation sets all parameters to their maximum values How...

Page 157: ...ion 15 Reserved MBZ 14 12 S0_RDLYCOL RW 1 Read delay from column address Used only when starting in page mode Delay from column address to latching first valid read data Programmed value desired value 02 11 9 S0_RDLYROW RW 1 Read delay from row address Delay from row address to latching first valid read data Programmed value desired value 04 8 7 S0_COLHOLD RW 1 Column hold tCAH from b0_cas 1 0 _l ...

Page 158: ...is illegal Programmed value desired value 01 3 2 S0_ROWHOLD Row address hold Used to switch memadr from row to column after b 1 0 _ras_l assertion Programmed value desired value 01 1 0 S0_ROWSETUP RW 1 Row address setup Used to generate b 1 0 _ras0_l assertion from row address Programmed value desired value 01 Timing register B is shown in Figure 6 18 and is defined in Table 6 8 Figure 6 18 Bank S...

Page 159: ...ay from b0_cas 1 0 _l deassertion to the next assertion of b0_cas 1 0 _l in page mode Programmed value desired value 01 5 3 S0_WTCAS RW 1 Write CAS width tCAS Used on write transactions to generate the b0_cas 1 0 _l deassertion from the assertion of b0_cas 1 0 _l The sum of S8_WTCAS and S0_TCP must not be greater than 5 Programmed value desired value 02 2 0 S0_RTCAS RW 1 Read CAS width tCAS Used o...

Page 160: ...en transactions is disabled 2 0 GTR_RP Minimum number of RAS precharge cycles Cycles extend from b 3 0 _ cas0_l deassertion to next assertion of the same b 3 0 _cas0_l pin Corresponds to DRAM parameter tRP Programmed value desired value 0 2 6 6 8 7 Refresh Timing Register The refresh timing register contains information used to refresh all bank sets simultaneously using CAS before RAS refresh Ther...

Page 161: ...r 14 13 Reserved MBZ 12 7 REF_INTERVAL RW 000001 Indicates the extent of the refresh interval Multiplied by 64 to get the number of memclk cycles between refresh requests A programmed value of zero is illegal 6 4 REF_RASWIDTH RW 1 Refresh RAS width Refresh RAS assertion width from b 3 0 _ras0_l assertion to b 3 0 _ras0_l deassertion b 3 0 _cas0_l is deasserted with b 3 0 _ras0_l for refresh Corres...

Page 162: ...sists of the buffers and their communications buses This section gives a functional overview of the 21071 BA chips that make up the data bus configuration Figure 6 21 shows a block diagram of the 21071 BA chip Figure 6 21 Block Diagram of the DECchip 21071 BA ML013459 PAD Latch sysData 127 0 DMA Write Buffer Memory Write Buffer memData 127 0 Merge I O Read Buffer Memory Read Buffer ECC Generator D...

Page 163: ...es for I O write data and two entries are for read data Each entry has four longwords but only two longwords are used the extra storage is not accessible The memory and cache controller 21071 CA handles the loading of the buffer using the address provided on iolinesel 1 0 by the PCI host bridge 21071 DA Each entry can be loaded separately allowing maximum flexibility in allocating the entries The ...

Page 164: ...DMA read transaction or a DMA masked write transaction If the data contains a correctable error the data path chips send corrected data to its destination DMA read buffer for DMA read transactions memory write buffer for DMA write transactions If the data contains an uncorrectable error dual bit ECC error the data path chips notify the PCI host bridge 21071 DA and writes the bad ECC error in the m...

Page 165: ...own in Figure 7 1 Figure 7 1 PCI Host Bridge PCI Host Bridge 21071 DA EpiData bus 32 Bits ML013280 PCI BUS 32 Bits As a PCI host bridge the 21071 DA chip contains all control functions of the bridge and some data path functions Figure 7 2 shows a block diagram of the 21071 DA chip PCI Host Bridge 7 1 ...

Page 166: ... acts as a master during the CPU initiated transactions that use the PCI bus and is a target of transactions initiated by other devices The PCI host bridge controls the buffers for various transactions The address and control mechanism is in the PCI host bridge the data is stored in the 21071 BA chips 7 1 Interface to the System Bus 7 1 1 Decoding Physical Addresses The PCI host bridge provides ad...

Page 167: ...write transactions a maximum burst length of two is supported in sparse memory and I O spaces and a maximum burst length of eight is supported in dense memory space On CPU initiated read transactions a maximum burst length of two is supported 7 2 Interface to the PCI bus 7 2 1 Decoding PCI Addresses When an entry in the DMA write buffer is unloaded the PCI host bridge translates the 32 bit PCI add...

Page 168: ... specifies the burst order The PCI host bridge stores the burst order in PCI address bits ad 1 0 When the PCI host bridge is a master of the PCI local bus it always specifies a linear incrementing burst order ad 1 0 0 On DMA transactions the PCI host bridge supports burst transfers only if a linear incrementing burst order is specified If the master specifies a different burst order that is ad 1 0...

Page 169: ...m lock flag on read and write transactions to system memory that are exclusive to the PCI bus Some data transfers require both the system bus and the PCI bus to complete For example CPU I O transfers require ownership of the system bus followed by ownership of the PCI bus In the same way PCI bus masters DMA transactions with the memory subsystem require ownership of the PCI followed by ownership o...

Page 170: ...mpleting any data transfers Until the lock is cleared only the PCI bus master that sent the latched transaction is allowed to complete transactions to main memory see the PCI Local Bus Specification In the system bus interface the lock causes the system lock flag to be cleared by using the ioclrlock command encoded on the iocmd 2 0 The system lock flag stays cleared until all latched transactions ...

Page 171: ...s ownership for extended periods of time and selects low latency instead of high throughput 7 3 9 Address Stepping in Configuration Cycles To provide flexibility and reduce design complexity when using the address stepping feature the PCI host bridge performs address stepping on configuration read and write transactions For these transactions the PCI host bridge drives the PCI bus for two clock cy...

Page 172: ...0 1 A000 01A0 Host address extension register 1 HAXR1 1 A000 01C0 Host address extension register 2 HAXR2 1 A000 01E0 PCI master latency timer register 1 A000 0200 TLB tag 0 register 1 A000 0220 TLB tag 1 register 1 A000 0240 TLB tag 2 register 1 A000 0260 TLB tag 3 register 1 A000 0280 TLB tag 4 register 1 A000 02A0 TLB tag 5 register 1 A000 02C0 TLB tag 6 register 1 A000 02E0 TLB tag 7 register ...

Page 173: ...d be written to unspecified bits within a CSR CSRs are initialized as shown in the Type column All CSRs are addressed on cache line boundaries that is address bits 4 2 must be zero In the implementation address bits 27 11 are treated as a don t care state Therefore accesses to addresses with nonzero address bits 27 11 map to the CSR address with address bits 27 11 equal to zero 7 5 1 Diagnostic Co...

Page 174: ...D CMRD NDEV TABT IOPE DDPE MBZ LOST IORT DPEC DCEI PENB MBZ TENB Table 7 2 Diagnostic Control Status Register Field Name Type Description 31 PASS2 RO Pass 2 Chip version reads low on pass 1 and high on pass 2 30 22 Reserved MBZ 21 18 PCMD RO PCI command Indicates the PCI type when a PCI initiated error is logged Valid only when IPTL NDEV TABT and IOPE are set continued on next page 7 10 PCI Host B...

Page 175: ...1 6 01 Reserved 10 Partial bypass DMA read transactions bypass buffered memory write transactions if the address within the page does not match that of the buffered DMA write transactions The address comparison is done across bits 12 6 11 No bypass DMA read bypassing is disabled DMA read transactions are ordered with respect to DMA write transactions originating on the PCI bus 15 MERR RW 0 Memory ...

Page 176: ...d when the data read from the DMA read buffer in the 21071 BA reaches the 21071 DA on a DMA read or scatter gather read transaction 11 NDEV RWC 0 No device This bit is set when devsel signal is not asserted in response to an I O read or write transaction initiated on the PCI by the 21071 DA Bits ad 31 0 are logged in the PCI error address register 10 TABT RWC 0 Target abort This bit is set when a ...

Page 177: ...eneration is not affected 3 DCEI RW 0 Disable correctable error interrupt When set correctable errors on DMA read data are not logged in the CMRD bit DCSR12 and the address is not updated in the system bus error address register This bit determines only whether the error is logged and if the processor is interrupted 2 PENB RWC 0 Prefetch enable bit When set the system bus master state machine enab...

Page 178: ... bits in the DCSR The register is valid only when one of these error bits is set If one of the bits is set a subsequent error of the same type will not update the address logged in this register and the LOST bit is set in DCSR 7 5 3 System Bus Error Address Register The system bus error address register holds the system bus address that was being used when an error happened The register is shown i...

Page 179: ...3 have no side effects on write transactions and they return zero on read transactions Use write transactions to these registers to pack the CPU s write buffers to prevent merging of sparse space I O write transactions If this mechanism is used software is not required to use memory barrier instructions between write transactions 7 5 5 Translated Base Registers 1 and 2 The translated base register...

Page 180: ... Reserved MBZ 7 5 6 PCI Base Registers 1 and 2 PCI base registers 1 and 2 provide the base address of the target window The registers are shown in Figure 7 7 and are defined in Table 7 6 Figure 7 7 PCI Base Registers 1 and 2 0x1A0000100 0x1A0000120 31 30 08 07 06 05 04 03 02 01 00 LJ 04199 AI PCI_BASE 31 20 WENB 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SGEN MBZ Table 7 6 PCI ...

Page 181: ...slated base 18 SGEN RW 0 Scatter gather enable When clear the PCI target window uses direct mapping to translate a PCI address to a CPU address When set the PCI target window uses scatter gather mapping to translate a PCI address to a CPU address 17 0 Reserved MBZ 7 5 7 PCI Mask Registers 1 and 2 PCI mask registers 1 and 2 define the size of the target window The registers are shown in Figure 7 8 ...

Page 182: ... shown in Figure 7 9 Figure 7 9 Host Address Extension Register 0 0x1A0000180 31 30 08 07 06 05 04 03 02 01 00 LJ 04201 AI Hardcoded to Zero 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 7 5 9 Host Address Extension Register 1 The host address extension register 1 generates ad 31 27 on CPU initiated transactions addressing PCI memory space The register is shown in Figure 7 10 and ...

Page 183: ...tions The register is shown in Figure 7 11 and is defined in Table 7 9 Figure 7 11 Host Address Extension Register 2 0x1A00001C0 31 30 08 07 06 05 04 03 02 01 00 LJ 04203 AI EADDR 7 0 MBZ 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CONF_ADDR 1 0 Table 7 9 Host Address Extension Register 2 Field Name Type Description 31 24 EADDR 7 0 RW 0 Extended address Used as the eight high or...

Page 184: ...3 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Table 7 10 PCI Master Latency Timer Register Field Name Type Description 31 8 Reserved MBZ 7 0 PMLC 7 0 PCI master latency time Loaded into the master latency timer register at the start of a PCI master transaction initiated by the 21071 DA The register resets to zero 7 5 12 TLB Tag Registers 0 Through 7 The TLB tag registers contain the PCI page a...

Page 185: ...ntry valid The entry valid bit can be read and written through this bit Normally the invalid bit contains the value read during a page table entry read transaction 11 0 Reserved MBZ 7 5 13 TLB Data Registers 0 Through 7 The TLB data registers contain the CPU page address associated with the PCI page address in the TLB tag registers The registers are shown in Figure 7 14 and are defined in Table 7 ...

Page 186: ... of the translated CPU address can be read or written through this field 0 Reserved MBZ 7 5 14 Translation Buffer Invalidate All Register 0x1A0000400 The translation buffer invalidate all register TBIA is write only A write transaction to this register invalidates all valid entries in the scatter gather map TLB 7 22 PCI Host Bridge ...

Page 187: ...he PCI bus is the base for the I O subsystem All I O components are connected by the 32 bit 5 V only PCI implementation and are called PCI devices Figure 8 1 shows a block diagram of the I O subsystem PCI bus 8 1 ...

Page 188: ...base address of each PCI device except the Nbus interface SIO is configured by the Digital Alpha VME 4 firmware Each base address is initialized by writing configuration registers located in PCI configuration space of the system address map The following components make up the I O subsystem and are PCI devices Ethernet controller interface to the network SCSI controller interface to SCSI devices P...

Page 189: ...ss to configuration registers and control status registers CSRs and behaves as a bus master when communicating with memory Refer to the DECchip 21040 AA specification for details of programming and use 8 1 1 PCI Configuration Registers CPU Address 0x1E0010000 0x1E0011FE0 PCI Address 0x00001000 0x000010FF The Ethernet controller responds to PCI configuration reads and writes to its configuration re...

Page 190: ...08 0000100C 00001010 00001014 00001018 00001028 0000102C 00001030 00001034 00001038 0000103C 00001040 00001044 to 000010FC ML013282 8 1 2 Ethernet Controller CSRs The Ethernet controller has 16 CSRs that can be accessed by the PCI host bridge The address field in Table 8 1 reflects the offset from the CSR base address CBIO CBMA The CSRs are located in PCI I O or memory space The CSRs are quadword ...

Page 191: ...SR13 SIA connectivity register xxxx xx68H CSR14 SIA Tx Rx register xxxx xx70H CSR15 SIA general register xxxx xx78H 8 1 3 PCI Cycles As a slave the Ethernet controller responds to single longword accesses in I O space and configuration space Burst writes to I O space cause target initiated retry termination of the cycle As a master the Ethernet controller performs DMA operations Its tenure on the ...

Page 192: ... SCSI Controller The SCSI controller is based on the NCR 53C810 chip For full operational programming details see the specification for the chip and the NCR 53C720 programming guide 8 2 1 Connection and Termination The SCSI bus is routed to the VMEbus P2 connector The pinning for the user defined pins of the connector is provided in Appendix A An interface to a standard SCSI cable is handled by th...

Page 193: ... configured in PCI space the programming of the NCR 53C810 chip is compatible with the NCR 53C720 chip For information on programming the NCR 53C720 chip see its programming guide 8 2 4 PCI Configuration Registers CPU Address 0x1E0020000 0x1E0021FE0 PCI Address 0x00002000 0x000020FF The SCSI controller has two base address registers one for I O and one for memory space This allows the 128 bytes of...

Page 194: ...Timer X X 00002000 00002004 00002008 0000200C 00002010 00002014 00002028 0000202C 00002030 00002034 00002038 0000203C 00002040 to 000020FC ML013284 X X 8 2 5 SCSI Control Status Registers The SCSI controller has 128 accessible bytewide CSRs as shown in Table 8 2 These registers are accessible starting at the following addresses SCSI_IO_BASE in PCI I O space SCSI_MEM_BASE in PCI memory space For in...

Page 195: ...8 SOCL R W Output Cntrl Latch 09 SSID R Selector ID 0A SBCL R W Bus Control Lines 0B DSTST R DMA Status 0C SSTAT0 R SCSI Status 0 0D SSTAT1 R SCSI Status 1 0E SSTAT2 R SCSI Status 2 0F DSA R W Data Structure Addr 10 13 ISTAT R W Interrupt Status 14 RESERVED 15 17 CTEST0 R W Chip Test 0 18 CTEST1 R Chip Test 1 19 CTEST2 R Chip Test 2 1A CTEST3 R Chip Test 3 1B TEMP R W Temporary Stack 1C 1F 20 CTES...

Page 196: ...dder 3C 3F SIEN0 R W SCSI Interrupt Enable 0 40 SIEN1 R W SCSI Interrupt Enable 1 41 SIST0 R SCSI Interrupt Status 0 42 SIST1 R SCSI Interrupt Status 1 43 SLPAR R W SCSI Longitudinal Parity 44 SWIDE R SCSI Wide Residue Data 45 46 47 STIME0 R W SCSI Timer 0 48 STIME1 R W SCSI Timer 1 49 STEST0 R SCSI Test 0 4C STEST1 R SCSI Test 1 4D STEST2 R W SCSI Test 2 4E STEST3 R W SCSI Test 3 4F SIDL R SCSI I...

Page 197: ...ird connector that allows I O access through the P2 connector PCI bus arbitration supports two PCI devices with up to four interrupt request lines each The PCI clock is driven from the Digital Alpha VME 4 assembly at a frequency of 32 MHz The card connectors provide 3 V and 5 V supply voltages Although you can have mixed supply voltages between cards the PCI bus signaling voltage must be 5 V The v...

Page 198: ......

Page 199: ...imple read and write cycles to the resources hanging off the Nbus lines as shown in Figure 9 1 Figure 9 1 Nbus and Nbus Resources Nbus Interface SIO Interrupt Controller Flash Super I O Keyboard and Mouse Controller Interval Timer TOY Clock Watchdog Timer NVRAM DS1386 Nbus 8 Bits ML013286 9 1 Nbus Address Space The bottom 64K of PCI sparse I O address space is mapped onto the Nbus for use by the K...

Page 200: ...s are the time of year TOY clock and the ROM Both of these regions are contiguous bytes When accessing the Nbus only one PCI byte enable is asserted 9 1 1 SIO Chip PCI Configuration Space CPU Address 0x1E0030000 0x1E0031FE0 PCI Configuration 0x00004000 0x000040FF The SIO chip does not have any base address registers Instead the SIO chip negatively decodes fixed regions in both PCI I O and PCI memo...

Page 201: ...9 1 1 1 PCI Control Register The PCI control register enables the SIO chip to respond to PCI IACK cycles and to set the expected assertion speed of the DEVSEL signal so that the subtractive decode sample point can be set The PCI posted write buffer is also enabled Table 9 1 lists the fields of the PCI control register Table 9 1 PCI Control Register Field Name Description 5 Must be set to a 1 defau...

Page 202: ...lpha VME 4 is 1001 representing one additional system clock tick 9 1 1 3 ISA Clock Divisor Register The ISA clock divisor register offset 4Dh is one of two bytewide registers used as the Nbus control word This register enables positive decode for BIOS ROM and the PCI to ISA clock divisor For Digital Alpha VME 4 the BIOS ROM region must not be positively decoded Bit 6 must be cleared and bits 2 0 m...

Page 203: ... 2 1 C001 0100 808 Memory configuration 3 1 C001 0120 809 Reset reason 1 1 C001 0140 80A Memory identification 1 C001 0160 80B Heartbeat clear interrupt 1 C001 0180 80C Module control 1 C001 01A0 80D Reset reason 2 1 C001 01C0 80E Bcache configuration 1 C001 01E0 80F Reset reason 3 1 C001 05C0 82E 9 2 1 Module Display Control Register CPU address 0x1C0010000 Nbus offset 0x800 The display is a 5x7 ...

Page 204: ...er while the least significant is along the top For example the character W is displayed by writing a value of 0x57 to the display register A value of 0xD7 displays W with full brightness After a system reset the display defaults to character 0x7F at full brightness During a system reset all dots in the matrix are lit Figure 9 4 Display Character Set 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 B L A N K 2...

Page 205: ... register Figure 9 5 Module Configuration Register 31 08 07 06 05 04 03 02 01 00 ML013288 Reserved CPU ID Don t Care MOD_CONFIG_REG Module ID Debug Mode Reserved Table 9 2 Module Configuration Register Field Name Type Description 1 0 Reserved 2 Debug RO If 0 the SROM starts the mini debugger If 1 the SROM starts the console 4 3 Module ID RO Identifies the I O module that is installed according to ...

Page 206: ...mory Configuration Registers 0 1 2 3 and Memory Identification Register Memory configuration 0 CPU address 0x1C00100C0 Nbus offset 0x806 Memory configuration 1 CPU address 0x1C00100E0 Nbus offset 0x807 Memory configuration 2 CPU address 0x1C0010100 Nbus offset 0x808 Memory configuration 3 CPU address 0x1C0010120 Nbus offset 0x809 0x1C0010160 0x80B The memory configuration and memory identification...

Page 207: ... 2 0 0 0 3 1 0 1 4 1 1 3 5 0 1 2 DRAM0 refers to the DIMM array containing memory data lines 0 63 DRAM1 refers to the DIMM array containing memory data lines 64 127 Tables 9 4 and 9 5 show the decode of the presence detect and ID bits stored in these registers Figure 9 6 Memory Configuration Registers 0 3 31 08 07 06 05 04 03 02 01 00 ML013315 Presence Detect Bits 1 8 Don t Care MEM_CONFIG_0 MEM_C...

Page 208: ...ification Register 31 08 07 06 05 04 03 02 01 00 ML013316 Bank 1 DRAM1 ID1 Bank 1 DRAM1 ID0 Don t Care MEM_ID_REG Bank 1 DRAM0 ID1 Bank 1 DRAM0 ID0 Bank 0 DRAM1 ID1 Bank 0 DRAM1 ID0 Bank 0 DRAM0 ID1 Bank 0 DRAM0 ID0 9 10 Nbus ...

Page 209: ... 1 2M x 72 80 1M x 4 16 10 10 16 128 1 0 1 1 4M x 72 4M x 4 12 11 64 256 1 0 1 1 4M x 80 4M x 4 12 10 64 256 4 PD 5 Controls data mode access according to the following values PD5 Definition 0 Fast page 1 Fast page with EDO 6 5 PD 7 6 Controls speed according to the following values PD 7 PD 6 Speed 0 1 80 ns 1 0 70 ns 1 1 60 ns 0 0 50 ns 0 1 40 ns 7 PD 8 Used to define memory DIMM configuration se...

Page 210: ...ion Bit PD8 IDO Description 1 0 x64 1 1 x72 Parity 0 0 x72 ECC 0 1 x80 ECC 9 2 5 Reset Reason Registers Reset reason 1 CPU address 0x1C0010140 Nbus offset 0x80A Reset reason 2 CPU address 0x1C00101C0 Nbus offset 0x80E Reset reason 3 CPU address 0x1C00105C0 Nbus offset 0x82E The reset reason registers record the cause of a module reset The cause can be one of the following Power up VME reset Front ...

Page 211: ...el Switch Watchdog Don t Care 80E 31 05 04 03 02 01 00 Don t Care 80A R WC RO R WS RO Read Only R W Read Writable R WC Readable Write to Clear R WS Readable Write to Set Table 9 7 Reset Reason Registers Field Name Type Description 0 Watchdog timer 0x80A R W to clear 0x80E Read Only 82E R W to set This is set immediately when a watchdog timer timeout occurs Available to indicate the HALT reason bef...

Page 212: ...tbeat clock is enabled in the TOY clock chip each active low to high at a frequency of 1024 Hz transition sets the heartbeat status bit This bit is not directly readable but it drives the heartbeat interrupt line into interrupt register 1 5 Writing data independent to the heartbeat clear interrupt register clears the heartbeat status bit and dismisses the interrupt request 9 2 7 Module Control Reg...

Page 213: ...ivides the segments in half These two bits default to 00 at power up selecting the device containing the console image in the bottom 512 KB The remaining 3 5 MB is available for user flash 2 Flash Write Enable Default at power up is 0 When set to 1 this bit asserts write enable to the four flash ROMs to allow updates To avoid corrupting the flash ROMs keep this bit cleared 0 when not updating 3 Fl...

Page 214: ...in the 82C54 can only operate in modes 0 and 3 When set the polarity of the TIMER0 gate input of the 8254 timer chip is inverted allowing proper operation in modes 1 and 5 9 2 8 Bcache Configuration Register CPU address 0x1C00101E0 Nbus offset 0x80F The Bcache configuration register shows the size and speed of the backup cache The values in this register are determined at installation by setting j...

Page 215: ... code is as follows Verify the processor operation Identify the reset type Find 2 MB of good memory Check the ability to read system ROM checksum Decompress 512 KB of ROM initialization code into memory Transfer control to initialization code The SROM is socketed to allow future firmware upgrades System ROM flash CPU address 0x200000000 PCI sparse memory address ROM_BASE_ADDR 0x00000000 The flash ...

Page 216: ...tch bit 3 of the module control register must be set to enable flash updates 9 4 Super I O Chip The FDC37C665GT Super I O SIO chip supports two 16550 UARTS channel A and channel B and one parallel port It provides FIFO for serial ports and EPP ECP modes for the parallel port For more information on the SIO chip and its operation see SMC s FDC37C665GT Super I O Specification 9 4 1 Serial Port Chann...

Page 217: ...ple writing an index value of 1 to address 398 selects the function address register If a read transaction from address 399 follows the data associated with the function address register is returned If a write transaction to address 399 follows the function address register is updated Table 9 10 Super I O Register Address Space Map Address Offset Read Write Physical Address Register General Regist...

Page 218: ... register 2FD 1 C000 5FA0 COM2 line status register 2FE 1 C000 5FC0 COM2 modem status register 2FF 1 C000 5FE0 COM2 scratch pad register COM1 Serial Port Registers 3F8 R 0DLAB 0 1 C000 7F00 COM1 receiver buffer register 3F8 W 0DLAB 0 1 C000 7F00 COM1 transmitter holding register 3F8 0DLAB 1 1 C000 7F00 COM1 divisor latch register LSB 3F9 1DLAB 0 1 C000 7F20 COM1 interrupt enable register 3F9 1DLAB...

Page 219: ...t Sector count 1F3 1 C000 3E60 Sector number Sector number 1F4 1 C000 3E80 Cylinder low Cylinder low 1F5 1 C000 3EA0 Cylinder high Cylinder high 1F6 1 C000 3EC0 Drive head Drive head 1F7 1 C000 3EE0 Status Command 3F6 1 C000 7EC0 Alternate status Device control 3F7 1 C000 7EE0 Drive address Not used 9 5 Keyboard and Mouse Controller CPU Address 0x1C0000C00 0x1C0000C80 Nbus offset 0x0060 0x0064 The...

Page 220: ...and SRAM functionality described in Sections 9 8 and 9 9 The square wave output of the chip generates a fixed 1024 Hz interval interrupt Timekeeping accuracy is better than 1 minute month at 25 C Timekeeping is maintained in the absence of Vcc by an internal lithium energy cell which has an active life of at least 10 years In addition the device internally protects against spurious accesses during...

Page 221: ..._ADDR 08 Date 0 4 TOY_BASE_ADDR 09 Month 0 7 TOY_BASE_ADDR 0A Year These registers are also used to control the following Field Register Description 6 TOY_BASE_ADDR 04 Specifies the format of the Hour unit When clear hours are stored as BCD from 0x00 to 0x23 When set the format is 12 hour that is the hours are 01 to 12 5 Used with 6 1 When clear hours are AM When set hours are PM 6 TOY_BASE_ADDR 0...

Page 222: ...OY_BASE_ADDR 03 TOY_BASE_ADDR 05 TOY_BASE_ADDR 07 9 6 2 TOY Clock Command Register The TOY clock command register located at TOY_BASE_ADDR 0B controls the operation of the TOY clock Figure 9 12 shows this register Figure 9 12 TOY Clock Command Register 31 08 07 06 05 04 03 02 01 00 ML013293 Transfer Enable Watchdog Select Don t Care TOY_BASE_ADDR 0B Watchdog Assertion Pulse Level O P Watchdog Enab...

Page 223: ...erted and held asserted The interrupt request input is only deasserted by writing to the heartbeat clear interrupt register at address 0x80C on the Nbus 9 7 Interval Timing Registers CPU Address 0x1C0080000 0x1C00BFFE0 Nbus offset 0x4000 0x7FFF Digital Alpha VME 4 s timer counters are based on the 82C54 device For more detail on the 82C54 see the vendor DECchip specification The 82C54 is made up o...

Page 224: ... values the separate timer data registers are used TMR_BASE_ADDR 0x00 to 0x08 9 7 1 Interval Timing Control Register In the interval timing control register the control byte shown in Figure 9 13 defines the mode of operation of and provides access control to each individual timer Because only a single byte in the 82C54 address space is used to access the full 16 bit counter value two accesses are ...

Page 225: ...never a read or a write operation to that timer occurs When set all operations to the timer register are in the format set until a new mode is set by another control byte to the timer according to the following values Value Description 00 Latch count for read back 01 LSB only access mode 10 MSB only access mode 11 LSB MSB access mode 3 1 Defines the operational mode of the timer according to the f...

Page 226: ... C14 When Timer 0 makes a low to high transition its output causes the assertion of an interrupt request IRQ The IRQ can be dismissed by an access to the timer interrupt status register Timer 1 operates as a rate generator with its output being driven off module by P2 pin C12 This timer is clocked by a fixed 10 MHz The output is also routed directly to VIC local IRQ input 3 Timer 2 operates as a r...

Page 227: ...is problem has been corrected For timers 0 and 2 which can cause timer interrupts through the interrupt register 3 3 reported through the timer interrupt status register an output low to high transition is considered to be the timer expiration that causes a status bit to be set and if enabled the interrupt request to be asserted Timer 1 can cause an interrupt through the VIC64 chip local IRQ3 only...

Page 228: ...unter reaches 0 The one shot is retriggerable The output remains low for n clocks after any trigger The one shot pulse can be repeated without rewriting the same count into the counter Mode 3 Continuous Square Wave Output This mode generates a square wave output of period n clock ticks This output is usually used to generate a rate output or a regular interrupt request to the CPU For odd count val...

Page 229: ...k Gat Timer Clk Gat Timer Tmr_irq 5 Tmr_minor_ip L P2 pin C13 5 10MHz 5 Tmr_major_ip L P2 pin C14 The clock inputs to timer 1 and 2 are a fixed 10 MHz source The clock input of timer 0 is from a P2 pin TMR_MINOR_IP L only The gate inputs for timers 1 and 2 are permanently asserted This means that 82C54 modes 1 and 5 are disabled on timers 1 and 2 The timer 0 gate input is driven from P2 pin C13 th...

Page 230: ...m are level 9 7 5 Timer Interrupt Status Registers The timer interrupt status register is aliased as the bottom byte in two contiguous longwords as shown in Table 9 15 The action of the register is slightly different depending on the address at which it is accessed and whether the access is a read or a write Figure 9 16 shows the timer interrupt status register Figure 9 16 Timer Interrupt Status R...

Page 231: ... function correctly This timer is located on the same chip as the TOY clock The watchdog timer is initialized with some time value in the range 0 01 to 99 9 seconds If left unaccessed the timer decrements towards 0 If allowed to reach 0 the watchdog timer first halts the system jump to Halt entry firmware and then forces the module into hardware reset some 300 ms later The module can be maintained...

Page 232: ...he TOY clock s address space as shown in Figure 9 17 Figure 9 17 Watchdog Timer Registers 07 06 05 04 03 02 01 00 1 10 Sec 1 100 Sec Second TOY_BASE_ADDR 0C TOY_BASE_ADDR 0D ML013299 Within the TOY clock chip the interrupt line and the pulse level assertion of that interrupt line for the watchdog timer are selectable In addition the watchdog function can be enabled or disabled by the TOY clock com...

Page 233: ...g timer output to level rather than pulse for example an external enable which defaults to disabled on power up is included This bit is in the module control register see Figure 9 19 and described in Section 9 2 7 When the watchdog timer has been fully and correctly initialized this bit should be set to allow normal watchdog timer operation Figure 9 19 Watchdog Timer Module Control Register 31 08 ...

Page 234: ... This RAM is organized as contiguous bytes starting at TOY_BASE_ADDR 0x0E through TOY_BASE_ADDR 7FFF as shown in Figure 9 20 Figure 9 20 NVRAM Access 07 06 05 04 03 02 01 00 Read Write TOY_BASE_ADDR 000E TOY_BASE_ADDR 000F ML013302 Read Write Read Write TOY_BASE_ADDR 7FFF As for the TOY clock operation module switch 1 allows the VMEbus 5VSTDBY to be connected to the DS1386 giving RAM backup that i...

Page 235: ...m for instructions on configuring the VME interface The VME interface consists of the DC7407 chip the VIC64 chip the CY7C964 bus interfaces and the connectors to the VMEbus on the backplane Figure 10 1 shows a block diagram of the VME interface Figure 10 1 VME Interface Block Diagram ML013375 PCI Host Bridge PCI Bus 32 Bits Other PCI Devices VIC64 8 Bits VME Connectors 3x8 Bits CY79C964 3 Chips DC...

Page 236: ... two address windows to map from PCI memory space to VME address space VME_WINDOW_1 is a 512 MB address window positioned in PCI memory space divided into 2048 KB x 256 KB pages Each page is mapped to VME address space by its own scatter gather entry The scatter gather entries of the first 256 pages are also used to map the VME_WINDOW_2 pages VME_WINDOW_2 is a 64 MB address window positioned in PC...

Page 237: ... S G 255 S G 0 ML013378 Each page can be mapped to any one of the three VMEbus address spaces A32 A24 or A16 As shown in Figure 10 3 numerous pages can be mapped to the same VMEbus address to allow access to the same location with different modes The address modifier code is fully programmable for each page VME Interface 10 3 ...

Page 238: ...atter Gather Mapping 10 1 1 Outbound Scatter Gather Mapping The outbound scatter gather entries control and map all master accesses from Digital Alpha VME 4 to the VMEbus Figure 10 4 shows an outbound scatter gather entry and how the VMEbus address is formed from the VME page and the PCI address 10 4 VME Interface ...

Page 239: ...its 28 18 If the PCI memory cycle addresses VME_WINDOW_2 the scatter gather entry is identified by PCI address bits 25 18 Bits 31 18 of the scatter gather entry provide the page address VME address bits 31 18 of the corresponding VMEbus page PCI address bits 17 2 together with the PCI byte enables specify the byte address within that page Once the correct scatter gather entry is identified its val...

Page 240: ...visory Program 0Eh 0x Yes User Page 0Bh D64 08h 1x Yes Supervisory Page 0Fh D64 0Ch 11 A24 00 No User Data 39h 01 No User Program 3Ah 10 No Supervisory Data 3Dh 11 No Supervisory Program 3Eh 0x Yes User Page 3Bh D64 38h 1x Yes Supervisory Page 3Fh D64 3Ch 10 A16 0x No User Access 29h 1x No Supervisory Access 2Dh 00 User Defined AM codes VIC_AMSR 10 1 1 2 Read Modify Write When a scatter gather ent...

Page 241: ...a size Block transfers D16 D32 D64 data size 10 1 2 1 Single Mode Transfers Single D08 D16 and D32 data transfers are executed by individual accesses to either of the two VME address windows in PCI memory space The data size for the VME transfers are derived from the byte enabling of the corresponding PCI cycle 10 1 2 2 Block Mode Transfers A block mode DMA engine in the VME interface can be progr...

Page 242: ...able DMA Direction 1 Read 0 Write Don t Care VME_IF_BASE D4 Interleave Period 250 x value nS VIC_BTCR 0 08 0 Table 10 2 VIC Block Transfer Control Register Field Name Description 3 0 Interleave period 250xValue nanoseconds Specifies a delay between bus transfers of blocks to allow arbitration of the bus 4 DMA direction When set the direction is Read When clear the direction is Write 5 Not used 6 B...

Page 243: ...map to the target VMEbus address with the required PCI start address as the write data 4 Clear the DMA enable bit in the VIC_BTCR 5 Wait for completion notification The completion interrupt is enabled in the VIC status register VIC_DMAICR and its vector is generated by the VIC error group interrupt vector address register VIC_EGIVBR 10 1 3 Requesting the VMEbus When Digital Alpha VME 4 acts as the...

Page 244: ...e Figure 10 6 Mapping Pages of Memory from VMEbus to PCI Bus ML013376 4 GB Mem Space 8 Kb PCI A32 VME A24 A16 Scatter Gather Mapping 10 2 1 Decoding Addresses The VME to PCI address decoding is implemented using CY7C964 bus interfaces within the VME interface Three CY7C964 bus interfaces are accessed together in the VMEbus i f address base VIF_ABR and VMEbus i f address base mask VIF_MASK register...

Page 245: ...VIF_MASK at VME_IF_BASE 0x180 If a bit is set the address to base register bit is not used in the address comparison At least the top five bits of the A32 address match byte must be used for matching Bytes 1 through 3 of VIF_ABR and VIF_MASK are contained in CY7C964 elements These three bytes must be written simultaneously Byte 0 is not used and does not affect address recognition See the CY7C964 ...

Page 246: ...y Page Memory Addr 31 0 00 VME Addr 12 2 Swap 12 13 0 Table 10 3 VME Address Field Name Description 4 0 MBZ 5 Valid 8 6 Swap 9 Write Lock Limits slave accesses to read only that is a page can be write locked 10 Supervisor Access Only Restricts access to supervisory cycles only 11 PCI I O Mem Select When clear the default the VME master uses a PCI memory cycle to transfer VME data to the mapped mai...

Page 247: ...onitor CSR VIP_PMCSR shown in Figure 10 10 31 14 Memory Page PCI uses C BE 3 0 signals to specify which bytes are being accessed Table 10 4 PCI Address Field Description 1 0 Set to 00 to pad 12 2 VME Address 30 13 Memory Page that is bits 31 14 of the VME address 31 Set to 0 to force access to the lower 2GB of PCI memory space Configuration cycles are never initiated by the VME interface Figure 10...

Page 248: ...When accessed over the VMEbus they are located in A16 space by Byte 1 of the VMEbus i f address base register VIF_ABR They are also accessible from PCI memory space starting at address VME_IF_BASE 0x60 The interprocessor communication register map is shown in Table 10 6 10 2 3 1 Interprocessor Communication Registers Five of the general purpose registers the interprocessor communication registers ...

Page 249: ...p processor register ICGPR See the VIC64 specification for more complete details 10 2 3 3 Interprocessor Communication Module Switches The Interprocessor Communication Module Switches ICMSs are software writable switches that can be set over the VMEbus to interrupt a processor The module switches however are meant to be issued to a specific module Because the module switches are meant for a specif...

Page 250: ...Intercommunication register status Bits 4 0 are set when there is a write access to the corresponding ICR See the VIC64 specification for more complete details Interprocessor communication global switches ICGS Write Only A write to an odd address sets the switch a Write to an even address clears that switch 010 Clear global switch 0 011 Set global switch 0 012 Clear global switch 1 013 Set global ...

Page 251: ...ull VMEbus system controller in slot 1 The Digital Alpha VME 4 system is selected as a system controller at power up by the state of the module diagnostic in progress switch position 4 closed As a system controller the Digital Alpha VME 4 system provides the following functions Causes a global reset to the VME interface logic Controls VMEbus arbitration driving BGIOUT Priority PRI Round Robin RRS ...

Page 252: ...masters all implement a Fair Request scheme If any master does not obey the fairness scheme it can starve the masters further along the daisy chain Under the Fair Request scheme the Digital Alpha VME 4 system does not request the VMEbus for the duration of a fairness timeout period if any other master is requesting the VMEbus When the timeout period expires the Digital Alpha VME 4 system asserts i...

Page 253: ...0 has the lowest priority Round robin RRS 7 0 When a request is being handled on a bus request level n the next request to be handled is on level n 1 If a request is being handled on level 0 the next request to be handled is on level 3 Single level SGL 7 1 All bus requests are set to the same level 7 Works with a device s request level to specify the arbitration scheme When clear the arbitration s...

Page 254: ...are VME_IF_BASE D0 VIC_RCR 08 Table 10 8 VIC Release Control Register Field Name Description 5 0 DMA burst length Specifies the number of data transfers during a burst on the VMEbus For example a value of 4 means that 4 words are transferred in D16 or in D32 it means 4 longwords For D64 block mode operation the burst length value is multiplied by four to give the maximum number of data transfers b...

Page 255: ...m is reprogrammed to another release mode 10 3 2 System Clock Output As the system controller the Digital Alpha VME 4 system drives the system clock SYSCLK for the VMEbus The clock is a fixed 16 MHz clock with a nominal 50 10 duty cycle This 16 MHz timing has no fixed phase relationship with other bus timings 10 3 3 Timeout Timers 10 3 3 1 Arbitration Timers By default the Digital Alpha VME 4 syst...

Page 256: ...own in Figure 10 13 Figure 10 13 VMEbus Transfer Timeout Register 31 07 05 04 02 01 00 ML013344 VMEbus Timeout Local bus Timeout Don t Care VME_IF_BASE A0 Arb Timeout Status Include VME Time Acquisition VIC_TTR 08 Table 10 9 VMEbus Transfer Timeout Register Field Name Description 0 When set the local bus timer includes the time for VMEbus acquisition 1 Arbitration timeout status This bit is set wh...

Page 257: ...rminated by an error the VME interface signals a local bus timeout This condition sets a status bit in the VMEbus error status register VIC_BESR 10 3 4 VMEbus Interrupt Handling A Digital Alpha VME 4 system can act as a VMEbus interrupter as well as a VMEbus interrupt servicing agent as described in Chapter 11 As system controller the Digital Alpha VME 4 system drives the IACK daisy chain if the V...

Page 258: ...r example when 0 is set setting 4 asserts IRQ4 1 IRQ1 2 IRQ2 3 IRQ3 4 IRQ4 5 IRQ5 6 IRQ6 7 IRQ7 A Digital Alpha VME 4 system uses the Release On Acknowledge method for removal of its interrupt requests As an alternative the interrupt requests can be deasserted by writing to the same VMEbus interrupt request status register that is used to assert the IRQ lines When a Digital Alpha VME 4 system dete...

Page 259: ...VME_IF_BASE 0x00 provides enabling of priority encoding for this interrupt Figure 10 16 Figure 10 16 VMEbus Interrupter Interrupt Control Register 31 07 06 03 02 00 ML013347 Mask Encoded Priority 1 7 Don t Care VME_IF_BASE 00 VIC_IICR 1 1 1 1 08 Table 10 11 VMEbus Interrupter Interrupt Control Register Field Name Description 2 0 Priority Priority 1 7 6 3 1111 7 Mask When set no interrupt is genera...

Page 260: ...3 The following table defines the swap modes Table 10 12 Swap Modes Mode Type of Swap Description 0 No Swap No bytes are swapped and in transferring bytes from the little endian PCI to the big endian VMEbus the address of any byte as seen on the two buses remains the same 1 Byte Swap The bytes within words are swapped 2 Word Swap The words within longwords are swapped 3 Longword Swap Combination o...

Page 261: ... Add Big Endian Byte Add Little Endian Byte Add Big Endian Byte Add Little Endian Byte Add Big Endian Byte Add PCI longword transfers Little Endian D64 BLT transfer Big Endian D0 D32 A0 A32 000 011 100 111 000 111 a b c d e f g h e f g h a b c d Swapper Mode 3 D64 swap enabled time PCI longword transfers Little Endian D64 BLT transfer Big Endian ML013307 10 4 2 VIC64 Byte Swapping When transfers o...

Page 262: ...wapped in a similar way The single data transfers D64 are a special case The VIC64 chip packs the data to form quadwords in the CY7C964s and on the VMEbus Only full quadword block mode transfers are allowed in D64 mode Table 10 13 shows the local bus address and size signals used for the DC7407 s swap modes when the DC7407 is master of the local bus When consulting the table keep the following in ...

Page 263: ...contig Noncontig 00 11 0000 00 00 00 00 00 00 00 00 0101 Noncontig Noncontig Noncontig Noncontig 1010 Noncontig Noncontig Noncontig Noncontig 0110 Noncontig 01 10 01 10 Noncontig 0010 Noncontig 01 11 00 11 Noncontig 0100 Noncontig 00 11 01 11 Noncontig As a VMEbus slave or during DMA driven block mode transfers the VIC64 drives the local bus address lines and the DC7407 generates the byte enable c...

Page 264: ...are uses the following procedure to set up the VME interface for use with the default values for the DC7407 registers 1 Set up the three PCI base registers in the VME interface 2 Program scatter gather RAM as needed 3 Configure the VIC64 for initialization Some timing control register values are defined 4 Operate the VME interface 10 5 1 VME PCI Configuration Registers CPU Address 0x1E0000000 0x1E...

Page 265: ...base address of a window in PCI memory space is written into the register Only bits 31 29 are writable because the 512 MB window must be aligned on a natural boundary VME_SG_BASE 00000818 This register gives access to scatter gather RAM when the base address of a 128 KB window in PCI memory space is written into the register VME_WINDOW_2_BASE 0000081C This register gives access to VME address spac...

Page 266: ...ess space VME A24 23 13 16384 A32 inbound VME_SG_BASE 8K page of A32 VME address space into PCI address space VME A32 26 13 2048 outbound VME_SG_BASE 1E000h 256K page of PCI memory into VMEbus Depends on region used for master access VME_WINDOW PCI 28 18 VME_SUB_ WINDOW 64 MB PCI 25 18 10 5 3 Configuring the VIC64 The address map for the VIC64 places the VIC registers in byte 3 of a particular lon...

Page 267: ...ME 4 Bit 7 Local interrupt mask bit ICGSICR Bits 2 0 Local IPL for global switch interrupts Bit 3 Reserved must read as 1 Bits 7 4 Interrupt mask bit for ICGS 3 0 ICMSICR Bits 2 0 Local IPL for module switch interrupts Bit 3 Reserved must read as 1 Bits 7 4 Interrupt mask bit for ICMS 3 0 EGICR Bits 2 0 Local IPL for error group interrupts Bit 3 SYSFAIL asserted read only Bit 4 SYSFAIL interrupt m...

Page 268: ...erved must read as 1s Bit 6 Must be cleared by the processor after reset If enabled by LICR7 this bit being set asserts SYSFAIL on the VMEbus Bit 7 Read only ICR7 Bits 4 0 Read and write from the VMEbus or local bus These bits are set if the corresponding ICR is written Bit 5 Read only Bit 6 HALT and RESET control Bit 7 VME SYSFAIL mask must be set after reset if resets are not to be translated in...

Page 269: ...ts 7 5 Minimum PAS deasserted time Must be binary 110 BTDR Bit 0 Dual Path enable Must be set Bit 1 AMSR register Sets up user defined address modifier codes for block mode transfers Bit 2 Local bus 256 bus byte boundary Recommend this be set Bit 3 VME 256 bus crossing enabled Recommend this be set Bit 4 Enables D64 master operation Bit 5 Enable enhanced turbo mode Must be clear Bit 6 Enables D64 ...

Page 270: ...s 1 0 Accelerated transfer mode Must be set to binary 10 Bits 3 2 Must be binary 01 for A24 slave selection Bit 4 D32 enable Must be set in the Digital Alpha VME 4 system Bit 5 Supervisor access Bits 7 6 Periodic timer enable Must be binary 00 SS0CR1 Local bus timing values Must be 0x00 SS1CR0 Bits 1 0 Must be set to binary 10 accelerated transfer mode Bits 3 2 Must be binary 00 for A32 slave sele...

Page 271: ...l register 44 VIC_ICMSICR ICMS interrupt control register 48 VIC_EGICR Error group interrupt control register 4C VIC_ICGSIVBR ICGS vector base register 50 VIC_ICMSVBR ICMS vector base register 54 VIC_LIVBR Local interrupt vector base register 58 VIC_EGIVBR Error group interrupt vector base register 5C VIC_ICSR Interprocessor communications switch register 60 70 VIC_ICR0 4 Interprocessor communicat...

Page 272: ...0 Block transfer length register 0 E0 VIC_SRR System reset register E4 BTLR2 Block transfer length register 2 E8 FC Reserved locations 100 VIP_CR VME interface processor control register 104 VIP_BESR VME interface processor bus error status register 108 VIP_ICR VME interface processor interrupt control register 10C VIP_IRR VME interface processor interrupt reason register 110 VIP_HWIPL VME interfa...

Page 273: ... scatter gather cached control word 138 VIP_PCIERTADR VME interface processor PCI error target address register 13C VIP_PCIERTCBE VME interface processor PCI error target command byte enables register 140 VIP_PCIERIADR VME interface processor PCI error initiator address register 144 VIP_LERADR VME interface processor VME local bus error address register 148 17C Reserved locations 180 VIFMASK VMEbu...

Page 274: ...e cycles will cause a bus timeout error Posted master Write in the VIC64 CY964 Alpha VME CPU is being accessed as a VME slave Master block transfer is being initiated by a pseudo write to the VIC64 over the Local bus 10 7 2 VIC64 Errata A16 Master Cycles During Interleave The Cypress VIC64 00 Design Considerations document dated 22 February 1994 lists the following errata A16 master cycles during ...

Page 275: ...re 11 1 shows a block diagram of the interrupt logic Table 11 1 Table of CPU Interrupt Assignments CPU Interrupt Interrupt Source Description cpu_irq0 Interrupt registers 3 4 PCI device interrupts from SCSI Ethernet multifunction PMC options SIO chip and VME interrupts 3 1 cpu_irq1 Interrupt register 2 PCI device INTA from PMC options and VME interrupts 6 4 cpu_irq2 Interrupt register 1 VIP locati...

Page 276: ...Interrupt Controller CPU_IRQ3 CPU_IRQ2 CPU_IRQ1 CPU_IRQ0 CPU_IRQ4 CPU_IRQ5 CPU 21064A PCI Host Bridge VIPSTATUS IRQ VIPERROR IRQ ML013320 11 1 1 Xilinx Interrupt Controller The cpu_irq 3 0 are generated by four interrupt mask registers contained in a Xilinx FPGA as shown in Figures 11 2 through 11 5 cpu_irq3 is controlled by bits 3 0 in interrupt mask register 1 cpu_irq2 is controlled by bits 5 4 ...

Page 277: ...by writing a 0 The interrupt mask register is write only A read of the interrupt mask register returns the state of the interrupts regardless of which mask bits are set A 1 means that the interrupt source has asserted an interrupt Figure 11 2 Interrupt Mask Register 1 07 06 05 04 03 02 01 00 ML013317 Reserved 802 IMS Heartbeat Timer VME IPL5 Periodic Heartbeat Timer Interval Timer VME IPL6 VME Res...

Page 278: ... Alpha VME 4 system s use of the VIC64 chip as an interrupt controller is modified slightly by the operation of the DC7407 the SIO chip and the interrupt mask registers VMEbus interrupts are passed to the interrupt mask registers by the VIC64 interrupt priority lines Vectors returned from the VIC as system interrupt controller are pre pended using bits 10 8 with the interrupting IPL The VIC64 chip...

Page 279: ...terrupt is reported if many interrupts are pending When a VME interrupt is identified the CPU initiates a read of the VMEbus interface processor interrupt reason register VIP_IRR which is read to retrieve the vector from the VIC DC7407 The read of the VIP_IRR generates a local bus IACK cycle at the pins of the VIC64 chip When the VIC64 chip detects the IACK cycle it responds with the vector and IP...

Page 280: ...MSICR VIC_ICMSIVBR 9 VMEbus IRQ7 VIC_IRQ7ICR 8 VMEbus IRQ6 VIC_IRQ6ICR 7 VMEbus IRQ5 VIC_IRQ6ICR 6 VMEbus IRQ4 VIC_IRQ6ICR 5 VMEbus IRQ3 VIC_IRQ6ICR 4 VMEbus IRQ2 VIC_IRQ6ICR 3 VMEbus IRQ1 VIC_IRQ6ICR 2 DMS status VIC_DSICR VIC_EGIVBR 1 VME IACK VIC_IICR VIC_EGIVBR 11 1 3 VIC64 Chip Interrupt Sources The following sections describe the VIC64 chip interrupt sources 11 1 3 1 Local Device Interrupts ...

Page 281: ...re 11 8 shows the local interrupt vector base register Figure 11 8 VIC Local Interrupt Vector Base Register 31 08 07 06 05 04 03 02 01 00 ML013306 User Programmable Vector Base 000 Not Used 001 Not Used 010 DC7407 Status 011 Not Used 100 Not Used 101 Not Used 110 Not Used 111 DC7407 Error Don t Care VME_IF_BASE 54 VIC_LIVBR 11 1 3 2 VMEbus Interrupt Requests The VIC64 chip handles the standard sev...

Page 282: ...er the VIC64 chip initiates a VMEbus IACK cycle to retrieve the bus interrupter s vector The VMEbus vector response is passed back to the DECchip 21064A in response to the system read of the VIP_IRR register It is assumed that the VMEbus interrupter releases the IRQ line either on seeing the VME IACK or because of the action register write and so forth of the interrupt service routines ISRs 11 1 3...

Page 283: ...upon DMA completion Figure 11 10 DMA Status ICR 31 08 07 06 03 02 01 00 ML013309 Disable Don t Care Encoded Priority 1 7 VME_IF_BASE 20 VIC_DMASICR The second case is a grouping that encompasses the SYSFAIL assertion arbitration timeout write posting failure and ACFAIL conditions The ICR VIC_EGICR associated with this group see Figure 11 11 is different than the ICRs already discussed Here a singl...

Page 284: ...nce again there is an associated ICR VIC_VIICR see Figure 11 12 to set the IPL and allow the condition to be disabled from generating its local interrupt Figure 11 12 VMEbus Interrupter ICR 31 08 07 06 03 02 01 00 ML013311 Disable Don t Care Encoded Priority 1 7 VME_IF_BASE 00 VIC_IICR There is a single interrupt vector base register for the error group DMA and interrupter sees IACK interrupts see...

Page 285: ... VME 4 nonmaskable events halt and SERR are handled through the SIO chip which contains a status register that can be polled to determine the NMI reason This register is the NMI status and control register at PCI I O address 0x00000061 All NMI events should cause a jump to the console entry point without destroying the software context and SERR should report an error If the interrupt reason is a H...

Page 286: ...it 7 is set if a system SERR has occurred The interrupt in response to this event is enabled by clearing bit 2 of this register to a 0 Bit 7 can be cleared only by setting the SERR enable bit bit 2 to a 1 and then back to a 0 Always write this bit as a 0 6 HALT Status RO Bit 6 is set when either the watchdog timer expires and is enabled or the HALT switch is toggled This interrupt is enabled by cl...

Page 287: ...A interrupts the CPU using the int_hw0 signal when there are errors to report The 21071 DA chip does not distinguish between hard and soft errors when asserting the interrupt signal The 21071 DA chip responds to CPU read block commands directly to the interrupt acknowledge address space which triggers the 21071 DA chip to perform an interrupt acknowledge transaction on the PCI bus The interrupt ve...

Page 288: ... it issues a VME SYSRESET under software control If Switch 3 is open the VIC64 chip still resets all internal registers return to their default state current transactions are aborted but the module reset is not generated To allow detection of this condition VIC64 chip only reset the VME SYSRESET signal is tied to interrupt and interrupt mask register 3 0 11 14 System Interrupts ...

Page 289: ...are already proficient in using the UNIX operating system you can start using the console commands described in Chapter 13 12 1 About the Console The Digital Alpha VME 4 console is a hybrid of an OpenVMS console and a UNIX shell A shell is a command line interpreter the interface between the operator and the firmware The Digital Alpha VME 4 console s firmware includes three OpenVMS components cons...

Page 290: ... console prompt is a familiar one to OpenVMS users the triple angle prompt The set of commands consists of many UNIX like commands several OpenVMS like commands and a unique set of commands specifically developed for diagnostics and design verification environments Chapter 13 describes each of the commands Table 12 1 shows the most frequently used commands Table 12 1 Commonly Used Commands OpenVMS...

Page 291: ...ut until the specified string is found at the beginning of a line Form string Pipe Uses output of the first command as the input for the second command Form cmd1 cmd2 Sequence Runs the first command to completion before running second command Form cmd1 cmd2 Line continuation Continues the command on the next line The prompt changes to _ until the command is completed Form cmd1 _ cmd2 Line comment ...

Page 292: ... effect String String with substitution Passes the string after expanding wildcards and environment variables cmd Command substitution Treats the string as a command executes it and substitutes it in the resulting output 12 1 4 Using Flow Control The console uses the following reserved words if then else elif fi case in esac for while until do and done These words provide a limited number of flow ...

Page 293: ...tract an exit status from variable junk The variable is initialized with the console set command set junk 0 show junk junk 0 eval junk 0 if eval junk then echo true else echo false fi 0 true set junk 1 if eval junk then echo true else echo false fi 1 false set junk 2 if eval junk _ then echo true _ else echo false fi 2 false 12 2 Getting Information About the System The following commands are used...

Page 294: ...ed images of the console and full help in loadable versions of the console The brief help for a command is a one line description of the command s function and all possible options and arguments for the command With full help all the information provided in Chapter 13 for a command is displayed on the console However due to space restrictions in the firmware ROMs only brief help is available by de...

Page 295: ...in the following example help more This command sequence causes a screen of text to be displayed Press the spacebar to continue the display and press Ctrl C to terminate the display For an explanation of the symbols used to represent syntax get help on the help command itself using the following command help help 12 4 Examining and Depositing to Memory or System Registers A byte stream is similar ...

Page 296: ... 4 console command For example pmem 0 refers to the location in physical memory at offset zero that is physical address 0 If no device name is supplied the offset applies to the last device referenced pmem by default However in the remaining discussions the terms address and offset are used synonymously The examine and deposit commands act on a physical address You can specify the actual address o...

Page 297: ...0 pmem 3FFF000 00000001 You can abbreviate commands and you do not need to specify the device if you are referring to the default device The following example shows the deposit and examine in an abbreviated form The current device is still physical memory d 3fff000 abcdef12 Deposit new data there e 3fff000 Check it out pmem 3FFF000 ABCDEF12 The console commands can be qualified using the UNIX like...

Page 298: ... script 00000000 65 63 68 6f 20 27 64 2f 53 27 20 3e 24 24 73 73 echo d S ss 00000010 0a 65 63 68 6f 20 27 2d 2d 2d 27 20 3e 3e 24 24 echo 12 4 2 Examining Registers You can use the examine and deposit commands to refer to registers You must include the address for the registers in one of the following ways Symbolically for example r0 or ksp Explicitly as offsets within device address space for ex...

Page 299: ...pr 2 ASTSR 0000000000000000 e and the current ipr 2 ASTSR 0000000000000000 e and the previous one ipr 1 ASTEN 0000000000000000 e ksp Examine an IPR by name ipr 12 KSP 0000000000000F30 e and the next one ipr 13 ESP 0000000000000000 The examine and deposit commands support symbolic representation of the following processor registers Register Meaning pc Program counter sp Stack pointer ps Process sta...

Page 300: ...emory and then uses grep to filter the output d pmem 3fff000 0 n 8 Clear some memory d 3fff020 abcdef12 Drop in a target e 3fff000 n 8 Display memory pmem 3FFF000 0000000000000000 pmem 3FFF008 0000000000000000 pmem 3FFF010 0000000000000000 pmem 3FFF018 0000000000000000 pmem 3FFF020 00000000ABCDEF12 pmem 3FFF028 0000000000000000 pmem 3FFF030 0000000000000000 pmem 3FFF038 0000000000000000 pmem 3FFF0...

Page 301: ...oked with the console exer command reads data from block 0 of a disk Then two processes of the console memory test are created using the memtest command In all three cases the console immediately returns with the console prompt and awaits further commands show device See what devices are available dka0 2 0 1 0 dka0 dka0 eza0 0 0 0 0 EZA0 08 00 2B 1D 02 91 ezb0 0 0 1 0 EZB0 08 00 2B 1D 02 92 pka0 7...

Page 302: ...e ps command as the argument of the kill command ps grep memtest Find a process to kill 0000005c 00144b40 2 135733 00000001 0 memtest ready 00000059 0014c060 2 138258 00000001 0 memtest ready kill 59 Kill one of the memtests ps grep memtest Display our background tasks 0000005c 00144b40 2 135733 00000001 0 memtest ready 12 8 Creating Scripts A script is a file that contains console commands simila...

Page 303: ...u use the first grouping character to open the character string and take as many lines as needed to create the script before entering the closing grouping character The following example shows how to create a long script using grouping characters echo foo ex 3fff000 _ d 3fff000 7 _ e 3fff000 _ d 3fff000 5 _ e 3fff000 cat foo ex 3fff000 d 3fff000 7 e 3fff000 d 3fff000 5 e 3fff000 foo pmem 3FFF000 0...

Page 304: ...OP server s load file directory MOP LOAD Whenever MOP gets a request for the script it searches in its service area At this point the script file is available on the Ethernet segment of the MOP server If the Digital Alpha VME 4 system is on the same Ethernet segment as the MOP server the following example copies the script file over the network The string mopdl sample sys eza0 specifies that the f...

Page 305: ... cat sample show version ls l sample sample version V1 1 0 Jul 1 1996 10 16 59 rwx rd 512 2048 0 sample Console Primer 12 17 ...

Page 306: ...file clear envar dynamic h v c z ha echo n args eval postfix_expression exit exit_value grep v c n y x f filename expression file kill pid ls l file more n pagesize file ps In this summary the following conventions are used item indicates the item is optional a b c indicates any one of a b or c a b c indicates any combination of a b or c device specifies the name of the driver for a device address...

Page 307: ...l blocks bs blocksize bc block_per_io d1 buf1_string d2 buf2_string a action_string sec seconds m v device free address memtest sa address ea address l length bs block size i inc p n f m z h rs n rb mb net sa s i ri ic se re rc l1 l2 els kls l file_name id node_address lc number l0 node_address bd burst_interval cm mode_string sv mop_version port nettest f filename mode string p n sv mop_version t...

Page 308: ...Table 12 3 Cont Digital Alpha VME 4 Console Command Summary Command Options Parameters Unique Console Commands sp process_id new_ priority stop device_path 12 20 Console Primer ...

Page 309: ... operating system and applications running at the time this could damage application files You enter the operating system command to go to console mode The operating system executes a HALT instruction The operating system encounters a fatal error The watchdog timer is enabled and the system software allows the timer to time out To leave console mode use the boot or start commands The code that sup...

Page 310: ...minal port can look for this character string to determine when to respond Commands are limited to 80 characters Characters entered after the 80th character replace the last character in the buffer Depending on your terminal these lost characters may be displayed but they are not included in the actual command line The command interpreter is not case sensitive Lowercase ASCII characters a through ...

Page 311: ...13 1 4 Console Command Dictionary The following commands are supported by the Digital Alpha VME 4 console program Console Commands 13 3 ...

Page 312: ...ecifies the modulus hexadecimal for the beginning address of the requested block remainder Specifies the remainder hexadecimal used in conjunction with the modulus for computing the beginning address of the requested block Options flood Flood memory with 0s By default the alloc command does not flood memory z heap_address Allocate memory from the memory zone starting at address heap_address You ca...

Page 313: ...alloc See Also dynamic free Console Commands 13 5 ...

Page 314: ... to set the default protocol for a given port Note Explicitly stating the boot flags or the boot device overrides the current default value for the current boot request but does not change the setting of the corresponding environment variable TFTP and BOOTP For the Internet environment the console implements Boot Protocol BOOTP and Trivial File Transfer Protocol TFTP clients to support network boo...

Page 315: ...th TCP IP Vol I Principles Protocols and Architecture Second edition Prentice Hall The following list shows the priority of the different ways of Internet booting from an initialized system 1 Specify the file name as the named boot boot file filename ewa0 If the pathname includes a slash it must be specified as a double slash For example boot file var adm ris ris0 alpha vmunix ewa0 Use this method...

Page 316: ...e the following procedure to get the software running Note that each network interface has a complete set of variables of its own prefixed with the name of the interface The examples shown here use boot device EWA0 1 Define the environment variable EWA0_PROTOCOLS with the name of the boot protocol you want to enable You can use BOOTP TFTP and MOP If this variable is not defined all protocols are e...

Page 317: ...his is the default file name requested by TFTP The Internet addresses use Internet standard dotted decimal notation for example 16 123 16 53 3 Initialize the database The database is marked as initialized on the first occurrence of any of the following Invoking BOOTP Invoking TFTP The most common way for initializing the database is the invocation of TFTP When TFTP is invoked and the database has ...

Page 318: ...IT environment variable is set to BOOTP or NVRAM respectively TFTP BOOTP and ARP all use retransmission to improve robustness If an initial transmission is not answered appropriately the protocol software retransmits Each protocol has an environment variable to control the number of retries The variables are named EWA0_ARP_TRIES EWA0_BOOTP_TRIES and EWA0_TFTP_TRIES The default value of these is 3 ...

Page 319: ...hine always boots the same file EWA0_BOOTP_FILE can be left empty Use the TFTP protocol driver to read files across the network TFTP accepts one parameter the host address concatenated to the file name of the remote file to be read Specify the host address in dotted decimal notation Separate the address from the file with a colon A slash in a file name must be doubled The following example display...

Page 320: ...formation to the operating system protocols enet_protocol Specifies the Ethernet protocols to be used for the network boot You can specify either MOP or BOOTP If you specify both the firmware attempts to use each protocol to solicit a boot server halt Forces the bootstrap operation to halt and invoke the console program once the image is loaded and page tables and other data structures are set up ...

Page 321: ...a TCP IP BOOTP network boot from Ethernet port EWA0 5 boot flags 0 1 The system boots from the default boot device using boot flag settings 0 1 6 boot halt dka0 The system loads the operating system from the SCSI disk dka0 but remains in console mode See Also set show Console Commands 13 13 ...

Page 322: ... until loop Exits the current shell with a status or returns the status of the last command Syntax break break_level Arguments break_level Specifies the status code to be returned by the shell Example for i in 1 2 3 4 5 do echo i break done 1 13 14 Console Commands ...

Page 323: ... file2 Specifies the name of the input files to be copied Options l length Specifies the number of bytes decimal of each input file to copy Examples 1 echo foo this is a test cat foo this is a test Creates the file foo with the echo command and then uses the cat command to send the contents of the file to the standard output the console terminal screen 2 cat l 6 foo this i Sends the first 6 bytes ...

Page 324: ...tions A minus sign indicates to remove the specified attributes A plus sign indicates to add the specified attributes An equals sign indicates to set the specified attributes and clear all other attributes not included in the command r Sets or clears the read attribute w Sets or clears the write attribute x Sets or clears the execute attribute b Sets or clears the binary attribute z Sets or clears...

Page 325: ...ples 1 chmod x script Adds the executable attribute to the file script 2 chmod r errlog Sets the file errlog to read only 3 chmod w dk Makes all SCSI disks nonwriteable See Also chown ls l Console Commands 13 17 ...

Page 326: ...ess2 Specifies the hexadecimal address or list of addresses of allocated blocks for which ownership is to be changed Example chown ps grep idle find 0 alloc 200 The first argument to the chown command uses the ps command to display processes and pipes the output to the grep command to find the idle process The second argument to the chown command calls alloc 200 to return the starting address of t...

Page 327: ...ote Some environment variables such as BOOTDEF_DEV are permanent and cannot be deleted Syntax clear variable_name Arguments variable_name Specifies the name of the environment variable to be deleted Example clear foo Deletes the environment variable foo See Also set show Console Commands 13 19 ...

Page 328: ...ea is destroyed and lost forever If you do not want the console to prompt you before the log areas is cleared specify the nc command option Console error logging is completely independent of the operating system s error logging Syntax clear_log Options nc No confirmation when specified you are not prompted before the NVRAM log area is cleared Example clear_log Error Log data in NVRAM will be destr...

Page 329: ...ters for the console is as described in the DS1386 specification except that the year register contains the number of years 1858 This is done to retain compatibility with the openVMS and UNIX operating systems Syntax date yyyy mm dd hhmm ss Arguments yyyymmddhhmm ss Specifies the new date and time where yyyy 0000 9999 is the year mm 01 12 is the two digit month dd 01 31 is the two digit day hh 00 ...

Page 330: ...date Example date 199208031029 00 date 10 29 04 August 3 1992 13 22 Console Commands ...

Page 331: ...specify a conflicting device address or data size the console ignores the command and issues an error response Syntax d eposit 2 6 6 6 6 6 4 b w l q o h 3 7 7 7 7 7 5 2 6 6 6 4 physical virtual gpr fpr ipr 3 7 7 7 5 n count s step device address data Arguments device Specifies the device name or address space to access The following devices are supported pmem Physical memory vmem Virtual memory Al...

Page 332: ...OM toy DS1386 registers clock chip and NVRAM address Specifies the address into which the data is to be deposited The address can be any valid hexadecimal offset in the device s address space or it can be a symbolic address For hexadecimal addresses that start with f you must add a leading zero 0 to prevent recognition as a floating point register For example 0f0 is a valid memory address while f0...

Page 333: ...eferenced minus one Names the location last referenced by an examine or deposit Uses the data at the last location referenced by an examine or deposit as the address data The data to be deposited If the specified data is larger than the deposit data size the console ignores the command and issues an error If the specified data is smaller than the deposit data size it is padded with leading zeros b...

Page 334: ...essor registers Using this option is the same as specifying the ipr device n count Specifies the number hexadecimal of consecutive locations to modify The console deposits to the first address then to the specified number of succeeding addresses s step Specifies the address increment size hexadecimal The address increment size defaults to the data size but is overridden by the presence of this opt...

Page 335: ...deposit 4 d l n 10 s 200 pmem 0 8 Deposits 8 into the first longword of each of the first 17 pages in physical memory See Also examine Console Commands 13 27 ...

Page 336: ...rors This flag takes effect only if a consistency check is being done h Displays the headers of the blocks in the default heap or the heap specified with option z p Displays dynamic memory statistics on a per process basis v Performs a validation test on the default heap or the heap specified with option z setsize Sets the total memory in the system to the specified size Adds the memory to or subt...

Page 337: ...s bytes blocks bytes zation water 00097740 1048576 398 359520 17 689088 34 371872 3 dynamic h zone zone used used free free utili high address size blocks bytes blocks bytes zation water 00097740 1048576 392 359136 17 689472 34 389280 a 00097740 000E1600_001E0600 000E1608_001BF628 00000000 00097740 32 f 000E1600 0017E600_00097740 00189E68_00097748 FFFFFFFF 000E1600 643072 a 0017E600 001823C0_000E1...

Page 338: ...Syntax echo n args Arguments args Specifies the character strings to be displayed Options n Suppresses new lines from the command output Examples 1 echo this is a test this is a test Echo sends the character string to your console screen 2 echo n this is a test this is a test Echo sends the character string to your console screen but with no new line separating the string from the next console pro...

Page 339: ...e echoed _ to file foo until the closing single quote cat foo this is the simplest way to create a long file All characters will be echoed to file foo until the closing single quote Shows how you can use echo to create a file that is several lines long See Also cat Console Commands 13 31 ...

Page 340: ...rand2 The second numeric value to be evaluated operator One of the following Add the operands Subtract operand2 from operand1 Multiply the operands Divide operand1 by operand2 Options ib Indicates that the operands are binary values io Indicates that the operands are octal values id Indicates that the operands are decimal values ix Indicates that the operands are hexadecimal values 13 32 Console C...

Page 341: ...isplays the output as octal values d Displays the output as decimal values x Displays the output as hexadecimal values Examples 1 eval 5 10 15 The sum of 5 plus 10 is 15 2 eval ix d 5 10 21 The sum of 5 plus 0x10 is 21 decimal Console Commands 13 33 ...

Page 342: ...specified address and data size If you specify a conflicting device address or data size the console ignores the command and issues an error response The display line consists of the device name the hexadecimal address or offset within the device and the examined data also in hexadecimal The examine command uses the same options as the deposit command Additionally the examine command supports inst...

Page 343: ...e FEPROM toy DS1386 registers clock chip and NVRAM address Specifies the address into which the data is to be deposited The address may be any valid hexadecimal offset in the device s address space or it may be a symbolic address For hexadecimal addresses that start with f you must add a leading zero 0 to prevent recognition as a floating point register For example 0f0 is a valid memory address wh...

Page 344: ... the examine or deposit command For references to physical or virtual memory the location is the last address plus the size of the last reference For other address spaces the address is the last address referenced plus one Names the location immediately preceding the last location referenced by the examine or deposit command For references to physical or virtual memory the location is the last add...

Page 345: ...gisters Using this option is the same as specifying the gpr device fpr The address space is floating point registers Using this option is the same as specifying the fpr device ipr The address space is internal processor registers Using this option is the same as specifying the ipr device n count Specifies the number of consecutive locations to examine s step Specifies the address increment size he...

Page 346: ...000 gpr 00000008 R8 00000000 gpr 00000009 R9 801D9000 gpr 0000000A R10 00000000 gpr 0000000B R11 00000000 gpr 0000000C AP 00000000 Examine R7 plus the 5 following GPRs 7 examine ipr 11 ipr 00000011 SCBB 2004A000 Examine the SCBB internal processor register IPR 17 decimal 8 examine scbb ipr 00000011 SCBB 2004A000 Examine the SCBB using the symbolic name 9 examine pmem 0 pmem 00000000 00000000 Exami...

Page 347: ...examine 11 examine pmem 20040048 DB MFPR S 2B B 48 R1 Look at the next instruction See Also deposit Console Commands 13 39 ...

Page 348: ...An address range to test within the devices The packet size also known as the I O size which is the number of bytes read or written in each I O operation The number of passes to run The number of seconds to run A sequence of individual operations performed on the test devices You specify this with the action string option Syntax exer sb start_block eb end_block p pass_count l blocks bs block_size ...

Page 349: ...ult to 0x800 The maximum block size allowed with variable length block reads is 0x800 bytes bc block_per_io Specifies the number of blocks hexadecimal per I O operation The default is 1 d1 buf1_string Specifies a character string that is processed by the eval command and then loaded into buffer1 to initialize the buffer By default the buffer is loaded with alternating 5s and As hexadecimal d2 buf2...

Page 350: ...he set of random numbers generated is always over the same set of block range numbers s Sleep for the number of milliseconds specified by the delay option If the delay option is not present sleep for 1 millisecond Note Times reported in verbose mode are not necessarily accurate when this action character is used sec seconds Terminates the exercise after the specified number of seconds have elapsed...

Page 351: ... Number of blocks bs Block size in bytes bc Number of blocks in a packet where a packet is the amount of data transferred in one I O operation You can specify reading writing comparing buffers and other operations to occur in various combinations and sequences These operations are specified by a string of 1 character command codes known as the action string Specify the action string as an argument...

Page 352: ...ngth in blocks or the starting ending block address option arguments If neither the ending address nor the length options are specified then on each pass the number of bytes processed could vary depending on whether or not the file stream is being written to or just being read If the exer command does not write to the file stream the command reads until it reaches the EOF If the exer command is wr...

Page 353: ...nation the status returned is that of the last failed write read or compare operation regardless of subsequent successful I O operations Examples 1 exer dk p 0 secs 36000 Read all SCSI type disks for the entire length of each disk Repeat this until 36000 seconds 10 hours have elapsed All disks are read concurrently Each block read occurs at a random block number on each disk 2 exer l 2 dka0 Read b...

Page 354: ... report any discrepancies 6 Repeat steps 1 through 5 until enough packets have been written to satisfy the length requirement of 101 blocks 6 exer a r w Rc dka0 A nondestructive write test with packet sizes of 512 bytes The action string specifies the following sequence of operations 1 Set the current block address to a random block number on the disk 2 From the current block address on the disk r...

Page 355: ...s run 8 set myd 0 exer bs 1 bc a l a a w d1 myd myd 1 foo hd foo l a 00000000 01 02 03 04 05 06 07 08 09 0a Write a pattern of 01 02 03 0a to file foo 9 set myd 0 exer bs 1 bc 4 l a a w d1 myd myd 1 foo m foo exer completed packet IOs elapsed idle size IOs bytes read bytes written sec bytes sec seconds secs 4 3 0 10 3001 10001 0 0 hd foo 00000000 01 02 03 04 01 02 03 04 01 02 show myd myd 4 10 ech...

Page 356: ...exer See Also memexer 13 48 Console Commands ...

Page 357: ... last command executed Syntax exit exit_value Arguments exit_value Specifies the status code to be returned by the shell Examples 1 exit Exits returning the status of the previously executed command 2 exit 0 Exits with success status 3 test exit Runs test and exits if there is an error Console Commands 13 49 ...

Page 358: ...false false return failure status Returns a failure status Syntax false Example while false do echo foo done 13 50 Console Commands ...

Page 359: ...urned to the appropriate heap Syntax free address1 address2 Arguments address1 address2 Specifies an address hexadecimal or list of addresses of allocated blocks to be returned to the heap Example alloc 200 00FFFE00 free fffe00 free alloc 10 alloc 20 alloc 30 See Also alloc dynamic Console Commands 13 51 ...

Page 360: ...and supports the following metacharacters Matches the beginning of a line Matches the end of a line Matches any single character Matches a specified set of characters for example ABC matches A or B or C The following rules also apply for these sets A dash other than the first or last character denotes a range of characters A Z matches any uppercase letter If the first character of the set is then ...

Page 361: ...ches STDIN Options c Prints only the number of lines that matched i Ignores case in the search By default the grep command is case sensitive n Prints the line numbers of the matching lines v Prints all lines that do not contain the expression f file Take the regular expression from a file instead of the command line Examples 1 ps grep ewa0 0000001f 0019e220 3 2 ffffffff 0 mopcn_ewa0 waiting on mop...

Page 362: ...EFEFEFEFEF pmem FFFFF0 0000000000000000 pmem FFFFF8 EFEFEFEFEFEFEFEF e n 3 ffffe0 grep v 0000000000000000 pmem FFFFE0 EFEFEFEFEFEFEFEF pmem FFFFE8 EFEFEFEFEFEFEFEF pmem FFFFF8 EFEFEFEFEFEFEFEF free ffffe0 The grep command searches for all quadwords in a range of memory that are non zero 13 54 Console Commands ...

Page 363: ...echo n the quick brown fox jumped over the lazy dog foo hd foo 00000000 74 68 65 20 71 75 69 63 6B 20 62 72 6P 77 6E 20 the quick brown 00000010 66 6F 78 20 6A 75 6D 70 65 64 20 6F 76 65 72 20 fox jumped over 00000020 74 68 65 20 6C 61 7A 79 20 64 6F 67 the lazy dog 2 byte foo 00000000 74 68 65 20 71 75 69 63 6B 20 62 72 6P 77 6E 20 the quick brown 00000010 66 6F 78 20 6A 75 6D 70 65 64 20 6F 76 6...

Page 364: ...dog 4 long foo 00000000 20656874 63697571 7262206B 206E776F the quick brown 00000010 20786F66 706D756A 6F206465 20726576 fox jumped over 00000020 20656874 797A616C 676F6420 the lazy dog 5 quad foo 00000000 6369757120656874 206E776F7262206B the quick brown 00000010 706D756A20786F66 207265766F206465 fox jumped over 00000020 797A616C20656874 00000000676F6420 the lazy dog 13 56 Console Commands ...

Page 365: ...xpressions for the shell For more information on regular expressions see the grep command Help topics are case sensitive When the help command describes command syntax the following conventions are used item Angle brackets denote a variable for which you must specify a value item Square brackets enclose optional parameters options or values a b c Braces enclosing items separated by commas indicate...

Page 366: ...elp 2 help List all topics and associated text Requests help on all topics 3 help ex Requests help on all commands that begin with ex 4 help boot Requests help on the boot command 13 58 Console Commands ...

Page 367: ... reset the system or issue the init command to set the environment variables to their default values Syntax init_ev Example init_ev Note A System Reset or init command must be issued immediately after this command to set all environment variables to their default values A system reset or the init command is now required Console Commands 13 59 ...

Page 368: ...izes the console a device or the processor Syntax init ialize c d device Options c Specifies that the console be initialized d device Specifies a device to be initialized Examples 1 init Initializes the processor 2 initialize d ewa0 Initializes device EWA0 13 60 Console Commands ...

Page 369: ...id2 Specifies the PIDs of the processes to be killed You can display PIDs with the ps command Example memtest p 0 ps grep memtest 000000f1 00217920 2 9357 ffffffff 0 memtest ready kill f1 ps grep memtest Runs memtest Displays the test s PID f1 with the ps and grep commands Deletes the process with the kill command Displays the memtest process again to show that it is now gone See Also ps Console C...

Page 370: ...while in a for while until loop Syntax line Examples 1 line type a line of input followed by carriage return type a line of input followed by carriage return The line you typed is copied to your screen 2 line foo type a line of input followed by carriage return cat foo type a line of input followed by carriage return Shows the line command used interactively 3 echo n continue Y N line tt tee foo n...

Page 371: ...isted If you omit the argument the command lists all files and inodes on the system Options l Lists the files or inodes in long format Each file or inode is listed on a line with additional information By default the command lists just file names Examples 1 ls examine examine Lists the file named examine 2 ls d d date debug1 debug2 decode deposit dg_pidlist dka0 0 0 0 0 dke100 1 0 4 0 dub0 0 0 1 0...

Page 372: ...ailable memory The pass count is 0 to run the tests forever Nothing is displayed unless an error occurs Syntax memexer number_of_tests Arguments number_of_tests Specifies the number of memory test processes to start The default is 1 Example memexer 2 Starts two memory tests running in the background Tests in blocks of 2 times the backup cache size across all available memory See Also memtest 13 64...

Page 373: ...c function s header information Therefore if you request a starting address of 0xa00000 and a length of 0x100000 the command reserves the area from 0x9fffe0 through 0xb00000 This is transparent to the user but could be confusing if you begin two memtest processes simultaneously with one beginning at 0xa00000 for a length of 0x100000 and the other at 0xb00000 for a length of 0x100000 In this case t...

Page 374: ...st 1 Writes the data pattern entered or default beginning at the starting address and marching through for the entire length specified 2 Begins again at the starting address reads the previously written data pattern and writes back its inverse This is done a longword at a time for the entire specified length 3 Begins at the end of the testing region and again reads back the previously written inve...

Page 375: ...data back into the random address 7 Compares the data written and the data read In the case of quadword write and read operations the longword of random data is shifted left by 32 and ORd with the original data s compliment to form the quadword Memtest test 4 Victim Eject Test You must first set up a block of data to be used in the test The address of this block of data is be read as an input to t...

Page 376: ...ngth of the section to test in bytes The default is BLOCK_SIZE except with the rb option which uses the zone size The l option has precedence over the ea option bs block_size Specifies the block size hexadecimal in bytes The default is 8192 bytes This is only used for the random block test For all other tests the block size equals length i address_inc This value is used to increment through the me...

Page 377: ...ified memory address without an allocation This bypasses all checking but allows testing in addresses outside of the main memory heap It also allows unaligned testing Caution This flag permits testing and corrupting any memory h Allocates test memory from the firmware heap mb Uses memory barriers after each memory access Use this option only in the f graycode test When this flag is specified an Al...

Page 378: ... without verification After each read and write to memory a memory barrier MB instruction is executed mb 5 memtest sa 200000 ea 400000 rb Tests memory from 0x200000 to 0x3fffff Every block within this range is randomly allocated rb Note The memtest command does not generate an error with the rb option if a block within the range cannot be allocated 6 memtest h rb bs 100 Tests the console heap h by...

Page 379: ...memtest See Also memexer Console Commands 13 71 ...

Page 380: ...to isolate network failures To display the Ethernet station address enter net sa ewa0 Syntax net s sa ri ic id l0 l1 rb csr els kls cm mode_string da node_address l file_name lw wait_in_secs sv mop_version port_name Arguments port_name Specifies the Ethernet port on which to operate If you do not specify a port the default port EWA0 is used Options s Displays port status information including MOP ...

Page 381: ... design verification test DVT loop service kls Kills the extended DVT loop service cm mode_string Changes the mode of the port device The mode string can be one of the following abbreviations nm Normal mode in Internal loopback ex External loopback nf Normal filter pr Promiscuous mc Multicast ip Internal loopback and promiscuous fc Force collisions nofc Do not force collisions df Default da node_a...

Page 382: ... 0 TO 0 RWT 39967 RHF 39969 TC 54 PORT INFO tx full 0 tx index in 10 tx index out 10 rx index in 11 MOP BLOCK Network list size 0 MOP COUNTERS Time since zeroed Secs 2815 TX Bytes 116588 Frames 204 Deferred 2 One collision 52 Multi collisions 14 TX Failures Excessive collisions 0 Carrier check 0 Short circuit 0 Open circuit 0 Long frame 0 Remote defer 0 Collision detect 0 RX Bytes 116564 Frames 19...

Page 383: ...00013 0011ac20 2 0 ffffffff 0 mopdl_ewa0 waiting on mop_ewa0_dlw 00000012 0011f6a0 6 0 ffffffff 0 tx_ewa0 waiting on ewa0_isr_tx 00000011 00121140 6 0 ffffffff 0 rx_ewa0 waiting on ewa0_isr_rx 00000010 00122ac0 1 0 ffffffff 0 pua_poll waiting on tqe 0000000f 001244e0 6 0 ffffffff 0 pua_receive waiting on pua_receive 00000009 00147460 5 0 ffffffff 0 lad_poll waiting on tqe 00000008 00148f00 5 0 fff...

Page 384: ...n power on diagnostics Runs the power on diagnostics script The pwrup command initializes network environment variables and runs memory tests Syntax pwrup Example pwrup Runs the power on script 13 76 Console Commands ...

Page 385: ... returned to the heap Syntax rm file1 file2 Arguments file1 file2 Specifies the files to be deleted Example ls foo foo rm foo ls foo foo no such file Lists file foo to show that it exists removes file foo lists file foo again to show that it is gone See Also cat ls Console Commands 13 77 ...

Page 386: ... process ID PID of the process to be modified affinity_mask Specifies the new affinity mask which indicates on which processors the process can run Bits 0 and 1 of the mask correspond to processors 0 and 1 respectively Example memtest p 0 ps grep memtest 00000025 001a9700 2 23691 00000001 0 memtest ready sa 25 2 ps grep memtest 00000025 001a9700 2 125955 00000002 1 memtest running See Also ps sp 1...

Page 387: ...phore queue Syntax semaphore Example semaphore Name Value Address First Waiter dyn_sync 00000001 00050378 dyn_release 00000001 000503A0 shell_iolock 00000001 0015D684 exit_iolock 00000001 0015D770 grep_iolock 00000001 0015DB20 eval_iolock 00000001 0015DC0C chmod_iolock 00000001 0015DCF8 C Console Commands 13 79 ...

Page 388: ... in Table 3 2 and the descriptions of commonly used environment variables below value Specifies the value to be assigned to the environment variable The value can be a numeric value or an ASCII string Options default Restores an environment variable to its default value integer Creates an environment variable as an integer string Creates an environment variable as a string Commonly Used Environmen...

Page 389: ...alue indicates that you want the system to execute minimal console diagnostics 2 set VME_A16_BASE 0 set VME_A24_BASE a00000 set VME_A24_SIZE 400 set VME_A32_BASE 80000000 set VME_A32_SIZE 4000 Set the following The base address of the VMEbus A16 address space to be x0 The base address of the VMEbus A24 address space to be x0xa00000 The size of the VMEbus A24 address space to be 1 MB The base addre...

Page 390: ... power on 6 set BOOT_FILE avme sys Sets the file name to be used when the system s boot requires a file name to avme sys 7 set BOOT_OSFLAGS 0 1 Sets the system s default boot flags to 0 1 8 set foo 5 Creates environment variable foo and sets its value to 5 See Also clear show 13 82 Console Commands ...

Page 391: ...rguments char Specifies the character to display on the front panel LED Prefix metacharacters with a backslash Options b Specifies that the character be displayed in bright mode The default is dim mode Examples 1 set LED W b Displays an uppercase W on the LED panel at full brightness See Also show led Console Commands 13 83 ...

Page 392: ...OM Mini Console command wb This command sets either NVRAM location 0x8028 and or 0x8029 to zero and allows the console to start the next time you reset or power on the system Note If the I O module s debug jumper is installed the system displays the SROM Mini Debugger prompt every time you power on the system While in the SROM Mini Debugger you can start the SRM console by entering the st command ...

Page 393: ... s internal lithium battery is lengthened The next time the system is powered up the oscillator is automatically reenabled by the console and time is once again counted by the TOY device This command is for use by manufacturing at final test or by users who want to put the system into storage Note You must reset the time and date once the module is powered up after disabling the battery Syntax set...

Page 394: ...g Specifies a text string terminated with white space Options v Prints lines as they are read x Shows commands just before they are executed d Deletes STDIN when the shell is done l Traces the lexical analyzer shows tokens as they are recognized r Traces the parser shows rules as they execute p Traces the execution engine shows routines called 13 86 Console Commands ...

Page 395: ...art a new shell the new shell s prompt sh v foo execute command file foo and show lines as read in sh x foo print out commands as they are executed and after all substitutions have been performed Console Commands 13 87 ...

Page 396: ...dware restart parameter block HWRPB led Displays a character illuminated on the LED panel map Displays system virtual memory map mode Displays the current mode FASTBOOT or NOFASTBOOT pal Displays the version of PALcode version Displays the version of the console firmware envar Displays the value of the environment variable specified See the listing of predefined environment variables in Table 3 2 ...

Page 397: ...plays the additional parameters to be passed to system software language Displays the language in which system software and layered products are displayed Examples 1 show version version V1 1 0 Jul 1 1996 10 16 59 Displays the version of the firmware on a system 2 show auto_action boot Displays the default system power on action 3 show bootdef_dev ewa0 Displays a system s default boot device In th...

Page 398: ... PALcode V5 56 4 OSF PALcode X1 45 8 MEMORY 16 Meg of system memory System Controller VIC64 Enabled Hose 0 PCI slot 0 DECchip 7407 slot 1 DECchip 21040 AA ewa0 0 0 1 0 08 00 2B E4 E3 06 slot 2 NCR 53C810 pka0 7 0 2 0 SCSI Bus ID 7 dka0 0 0 2 0 RZ26L dka300 3 0 2 0 RZ26L dka500 5 0 2 0 RRD42 slot 3 Intel 82378IB slot 4 DECchip 21052 AA Displays the system s configuration 13 90 Console Commands ...

Page 399: ...rt The output displays the device name device ID device type and device internal firmware revision information if available Syntax show device device_name Arguments device_name Specifies the device name or an abbreviation of a device name When you use an abbreviation or wildcard all devices that match are shown Examples 1 show device dkc0 0 0 2 0 DKC0 RZ57 mke0 0 0 4 0 MKE0 TLZ04 ewa0 0 0 6 0 EWA0...

Page 400: ...0 0 0 2 0 DKC0 RZ57 mke0 0 0 4 0 MKE0 TLZ04 Displays all devices with k in the device name 4 show device dk Show SCSI disks dkc0 0 0 2 0 DKC0 RZ57 Displays all devices starting with dk all SCSI disks 5 show device mk Show SCSI tape drives mke0 0 0 4 0 MKE0 TLZ04 Displays all devices starting with mk all SCSI tapes 13 92 Console Commands ...

Page 401: ...show hwrpb show hwrpb display HWRPB Displays the address of the Alpha hardware restart parameter block HWRPB Syntax show hwrpb Example show hwrpb HWRPB is at 2000 Console Commands 13 93 ...

Page 402: ...led hex Options hex Displays the contents of the LED register If you do not specify hex the character being displayed is echoed to the console Examples 1 show led Displays the current character being displayed by the LED panel 2 show led hex Displays the contents of the LED register See Also set led 13 94 Console Commands ...

Page 403: ...map pte 00001020 v FFFFFC0902408000 p 00000000 V KR SR FR FW pte 00001028 v FFFFFC090240A000 p 00000000 V KR SR FW pte 00001020 v FFFFFC0902C08000 p 00000000 V KR SR FR FW pte 00001028 v FFFFFC0902C0A000 p 00000000 V KR SR FW pte 00001020 v FFFFFC0B02408000 p 00000000 V KR SR FR FW pte 00001028 v FFFFFC0B0240A000 p 00000000 V KR SR FW pte 00001020 v FFFFFC0B02C08000 p 00000000 V KR SR FR FW pte 00...

Page 404: ...RAM error log area The default value for count is 1 all Displays all faults logged into the NVRAM error log area All faults are marked as seen so that new faults can be easily displayed using the new option This command always displays all logged faults new Displays all new faults logged into the NVRAM error log area displays all faults that have not been previously displayed by the show_log all c...

Page 405: ... 0400000004000000 PC 0000000000064c40 F A U L T 2 Time of Error 13 08 39 9 AUG 1994 Diagnostic Interval Timer Pass Count 1 Test Number 4 Failing Point 18 Error Message Interrupt not invoked and should have been No more faults found Displays the two most recent faults since they are the only ones logged into NVRAM See Also clear_log Console Commands 13 97 ...

Page 406: ...bits Syntax sleep v time_in_secs Arguments time_in_secs Specifies the number of seconds to sleep The default is one second Options v Specifies that the value supplied is in milliseconds The default is 1000 one second Examples 1 sleep 10 echo hi there 10 seconds expire hi there Sleep for 10 seconds then execute the echo command 2 sleep v 20 Sleep for 20 milliseconds 13 98 Console Commands ...

Page 407: ...e of the file that sort can handle is limited by the size of memory Syntax sort file Arguments file Specifies the file to be sorted Examples 1 echo foo banana _ pear _ apple _ orange Create file foo with 4 lines 2 sort foo apple banana orange pear Sort file foo and send output to the console Console Commands 13 99 ...

Page 408: ...ifies the process ID PID of the process to be modified new_priority Specifies the new priority for the process Priority values range from 0 to 7 where 7 is the highest Example memtest p 0 ps grep memtest 00000025 001a9700 2 23691 00000001 0 memtest ready sp 25 3 ps grep memtest 00000025 001a9700 3 125955 00000001 0 memtest ready Raises the priority of process 25 from 2 to 3 See Also ps sa 13 100 C...

Page 409: ...fies the PC address at which to start execution Options drivers device_prefix Specifies the name of the device or device class to stop If no device prefix is specified then all drivers are started Examples 1 start 400 Starts program execution at address 400 2 start drivers Starts all the drivers in the system See Also continue init stop Console Commands 13 101 ...

Page 410: ...processor_num Specifies the processor to stop If you use this argument specify 0 Options drivers device_prefix Specifies the name of the device or the device class to stop If you do not specify a device prefix the command stops all drivers Example stop Stops the processor See Also continue init start 13 102 Console Commands ...

Page 411: ...onsole If the programming operation is successful a success message is displayed on the console Notes You must reset or cycle power on the system to run the new image in the FEPROMs otherwise the previous console image executes out of memory Be sure to disable FEPROM writing after completing the update process by setting switch 2 to the open position Syntax update file filename protocol transport ...

Page 412: ... NOT ATTEMPT TO INTERRUPT PROGRAM EXECUTION DOING SO MAY RESULT IN LOSS OF OPERABLE STATE The program will take at most several minutes Erasing the target flash device Erasure completed Programming Programming completed Verifying Update successful The example above shows how to do an update using the MOP protocol 2 update fi usr local bootfiles alphavme_v1_1 0 dev ewa0 tar console pro tftp update ...

Page 413: ...e at most several minutes Erasing the target flash device Erasure completed Programming Programming completed Verifying Update successful The example above shows how to do an update using the TFTP protocol Console Commands 13 105 ...

Page 414: ......

Page 415: ...24325 xx J12 P2 connector has the following power ground pin assignments Row A Row B Row C Ground 1 2 4 5 7 8 10 11 13 15 16 18 23 28 30 2 12 22 31 3 4 7 11 14 17 20 22 24 27 30 VCC 3 6 9 12 14 17 24 27 31 32 1 13 32 1 2 5 6 12 13 18 19 23 28 29 31 32 A 2 I O Type 1 Card Connector Pinouts Sections A 2 1 through A 2 3 show the pinouts for the VMEbus connector console and serial connectors and the E...

Page 416: ...9 SCSI_DP_L VME_A29 Ground 10 SCSI_ATN_L VME_A30 EXT_RESET_L 11 SCSI_BSY_L VME_A31 TMR2_EXT_OP_L 12 SCSI_ACK_L Ground TMR1_EXT_OP_L 13 SCSI_RST_L VCC TMR_MINOR_IP_L 14 SCSI_MSG_L VME_D16 TRM_MAJOR_IP_L 15 SCSI_SEL_L VME_D17 Ground 16 SCSI_CD_L VME_D18 PP_STB_L 17 SCSI_REQ_L VME_D19 PP_ERR_L 18 SCSI_IO_L VME_D20 PP_DATA0 19 Ground VME_D21 PP_DATA1 20 Ground VME_D22 PP_DATA2 21 Ground VME_D23 PP_DAT...

Page 417: ...2 Console J6 and Serial J7 Connector Pinouts Table A 2 lists the pinouts for the console J6 and serial J7 connectors Figure A 1 shows a pinout diagram Table A 2 Console J6 and Serial J7 Connector Pinouts Pin Signal 1 ready out 2 transmit 3 transmit 4 receive 5 receive 6 ready in Figure A 1 Console J6 and Serial J7 Connector Pinouts Pin 1 Pin 6 MLO 013549 Front view mating side Module Connector Pin...

Page 418: ... 2 Ethernet J9 Connector Pinouts Pin 8 Pin 1 Front view mating side MLO 013550 A 3 Primary Breakout Module Connector Pinouts Table A 4 lists the pinouts for the primary breakout module 54 24663 01 Figure A 3 shows a pinout diagram Table A 4 Primary Breakout Module Connector Pinouts Pin Row A Row B Row C 1 SCSI_DATA0_L VCC MSDATA 2 SCSI_DATA1_L Ground MSCLK 3 SCSI_DATA2_L N C Ground 4 SCSI_DATA3_L ...

Page 419: ... 13 SCSI_RST_L VCC TMR_MINOR_IP_L 14 SCSI_MSG_L N C TRM_MAJOR_IP_L 15 SCSI_SEL_L N C Ground 16 SCSI_CD_L N C PP_STB_L 17 SCSI_REQ_L N C PP_ERR_L 18 SCSI_IO_L N C PP_DATA0 19 Ground N C PP_DATA1 20 Ground N C PP_DATA2 21 Ground N C PP_DATA3 22 Ground Ground PP_DATA4 23 VME_MASTER_SW_L N C PP_DATA5 24 VCC N C PP_DATA6 25 VCC N C PP_DATA7 26 VCC N C PP_SLCT 27 VCC N C PP_PE 28 Ground N C PP_BUSY 29 G...

Page 420: ...A32 Side 2 C32 B32 A32 C1 B1 A1 C32 B32 A32 C1 B1 A1 J3 J4 MLO 013551 A 4 Secondary Breakout Module Connector Pinouts Figure A 4 shows the layout of the pinouts for the secondary breakout module Note the positions of the J1 keyboard and mouse and J6 parallel port connectors A 6 Module Connector Pinouts ...

Page 421: ...1 MLO 013552 P2 14 1 4 3 2 1 4 3 2 1 J4 J1 Sections A 4 1 and A 4 2 provide more detail on the J1 and J6 connectors respectively A 4 1 Keyboard and Mouse J1 Connector Pinouts Table A 5 lists the pinouts for the keyboard and mouse J1 connector Figure A 5 shows a pinout diagram Module Connector Pinouts A 7 ...

Page 422: ... 6 4 2 1 3 5 MLO 013553 Front view mating side A 4 2 Parallel Port J6 Connector Pinouts Table A 6 lists the pinouts for the parallel port J6 connector Figure A 6 shows a pinout diagram Table A 6 Parallel Port J6 Connector 1 PP_STB_L 2 PP_DATA0 3 PP_DATA1 4 PP_DATA2 5 PP_DATA3 6 PP_DATA4 7 PP_DATA5 8 PP_DATA6 continued on next page A 8 Module Connector Pinouts ...

Page 423: ... N C Figure A 6 Parallel Port J6 Connector Pinouts J6 J2 26 13 MLO 013554 14 1 Front view mating side A 5 PMC I O Companion Card Connector Pinouts Tables A 7 and Table A 8 list the pinouts for the PMC I O Companion Card 54 24665 01 mouse J2 and keyboard J3 connectors respectively Figure A 7 shows a pinout diagram for the connectors Module Connector Pinouts A 9 ...

Page 424: ...5 MOUSE_CLOCK 6 KBRD_CLOCK Table A 8 PMC I O Companion Card Keyboard J3 Connector Pin Signal 1 KBRD_DATA 2 MOUSE_DATA 3 Ground 4 VCC 5 KBRD_CLOCK 6 N C Figure A 7 PMC I O Companion Card Mouse J2 and Keyboard J3 Connector Pinouts 6 4 2 1 3 5 MLO 013553 Front view mating side A 10 Module Connector Pinouts ...

Page 425: ...r 5 14 generation of byte enable for 5 13 translation of 5 11 Addresses of keyboard mouse controller 9 22 of PCI bus decoding 7 3 Addresses cont d physical decoding of by PCI host bridge 7 2 stepping in configuration cycles 7 7 VME interface decoding 10 10 alloc command 13 4 Alpha VME CPU See Digital Alpha VME 4 Arbitration timeout 11 8 Arbitration timers 10 21 Arrow keys 13 2 AUTO_ACTION environm...

Page 426: ...21 keyboard 2 21 mouse 2 21 network 2 21 Cache 6 1 address of 6 1 data paths of 6 1 diagnostic tests for 4 3 modules required for 2 3 Cache cont d size tag enable values of 6 17 Cacheable address space 5 4 cat command 13 15 Character set display 9 6 CHAR_SET variable 3 4 chmod command 13 16 chown command 13 18 Circuit board module etch testing 4 10 clear command 13 19 clear_log command 13 20 Clock...

Page 427: ...13 2 rm 13 77 running in background 12 13 Commands cont d sa 13 78 semaphore 13 79 set 13 80 set led 13 83 set reboot srom 13 84 set toy sleep 13 85 sh 13 86 show 13 88 show config 13 90 show device 13 91 show hwrpb 13 93 show led 13 94 show map 13 95 show_log 13 96 sleep 13 98 sort 13 99 sp 13 100 special keys for 13 1 start 13 101 stop 13 102 summary of 12 18 table of 12 2 update 13 103 vip_diag...

Page 428: ...escription 3 2 figure 3 1 Control status registers CSRs address space of 6 8 diagnostic 7 9 Control status registers CSRs cont d PCI host bridge 7 9 address space of 7 7 SCSI controller 8 8 Counters 9 25 CPU addresses mapping to PCI space 5 1 connector pinouts A 1 interrupt assignments 11 1 PCI host bridge interrupts for 7 6 Ctrl C 13 2 Ctrl O 13 2 Ctrl Q 13 2 Ctrl R 13 2 Ctrl S 13 2 Ctrl U 13 1 C...

Page 429: ...1 4 17 Diagnostic commands nicsr_diag cont d with t 2 4 17 with t 3 4 17 niil_diag 4 16 vip_diag with t 1 4 28 with t 2 4 28 with t 3 4 28 with t 4 4 29 wdog_diag 4 27 Diagnostics 4 1 at installation 2 27 console commands table 4 3 test descriptions 4 8 to 4 30 console prompt 4 2 control status register 7 9 DALLAS DS1386 RAMified watchdog timekeeper tests 4 18 DECchip 21040 configuration register ...

Page 430: ...ental specifications 1 4 functional specifications 1 1 memory 1 2 network features 1 2 network interconnect 1 2 operating systems support 1 1 PCI expansion 1 2 performance 1 2 physical specifications 1 2 1 4 Digital Alpha VME 4 cont d power supply current and dissipation 1 4 processor 1 2 product description 1 1 resetting 11 13 SCSI 2 1 2 serial and parallel interfaces 1 2 supported switch setting...

Page 431: ...iable 3 5 EWA0_BOOTP_FILE environment variable 3 5 EWA0_BOOTP_SERVER environment variable 3 5 EWA0_BOOTP_TRIES environment variable 3 5 EWA0_DEF_GINETADDR environment variable 3 5 EWA0_DEF_INETADDR environment variable 3 5 EWA0_DEF_INETFILE environment variable 3 5 EWA0_DEF_SINETADDR environment variable 3 6 EWA0_INET_INIT environment variable 3 6 EWA0_LOOP_COUNT environment variable 3 6 EWA0_LOOP...

Page 432: ...1 Inbound scatter gather entry 10 12 Indicators front panel description 3 2 figure 3 1 initialize command 13 60 init_ev command 13 59 Installation 2 6 to 2 27 of main memory 2 10 of PMC I O companion card 2 23 of primary breakout module 2 1 2 15 2 18 of secondary breakout module 2 20 of system module 2 14 Internet booting hierarchy 13 7 Interprocessor communication 10 14 global switches 10 14 modu...

Page 433: ... ls command 13 63 M Master DMA transfer 10 9 memexer command 13 64 Memory 1 2 6 1 accessing data in 12 9 address of 6 1 bits testing 4 7 cache 2 12 configuration registers of 9 8 configurations 2 11 control registers of 6 20 data paths of 6 1 depositing data in 12 7 diagnostic test 4 7 diagnostic tests for 4 3 DMA write buffer 6 31 error handling for 6 32 examining 12 7 exerciser test 4 3 generati...

Page 434: ...sts 4 24 NCR810 command status register dump 4 24 command status register reset value test 4 25 command status register test 4 25 internal live bus loopback test 4 25 NCR810 cont d internal loopback test 4 25 interrupt test 4 26 PCI configuration register test 4 24 SCSI controller chip testing 4 24 ncr810_diag command with t 1 4 24 with t 2 4 24 with t 3 4 25 with t 4 4 25 with t 5 4 25 with t 6 4...

Page 435: ...er 7 20 master timeout for 7 7 parking on 7 6 PCI bus cont d primary address space of 5 8 configuration cycles to targets of 5 9 scatter gather map address for 5 19 page table entry in memory for 5 18 translation to system bus address 5 21 secondary address space of 5 8 sparse I O address space 5 5 byte enable generation of 5 7 translation of 5 6 sparse memory address space 5 11 generation of addr...

Page 436: ...data register 6 21 Presence detect low data regster 6 20 Primary breakout module connector pinouts A 4 installing 2 1 2 15 2 18 jumpers 2 17 Primary PCI bus address space of 5 8 decoding configuration addresses in 5 8 Printer attaching 2 4 Process killing 12 14 Processor 1 2 network interconnect 1 2 Processor page monitor CSR 10 13 Product description 1 1 Protocol drivers 13 11 ps command 13 75 pw...

Page 437: ...11 12 PCI bus base register 5 15 base registers 7 16 configuration registers 8 3 8 7 control register 9 3 error address register 7 13 mask register 5 15 Registers PCI bus cont d mask registers 7 17 master latency timer register 7 20 presence detect low data register 6 20 presense detect high data register 6 21 refresh timing register 6 28 reset reason registers 9 12 SCSI controller CSRs 8 8 summar...

Page 438: ...10 6 inbound 10 12 outbound 10 4 read modify write bit of 10 6 Scatter gather map address for 5 19 page table entry in memory for 5 18 translation to system bus address 5 21 Scatter gather mapping outbound 10 4 Scatter gather RAM programming 10 31 test 4 4 testing 4 28 4 29 Scripts copying over network 12 15 creating 12 14 SCSI controller 8 6 connection and termination 8 6 CSRs 8 8 ID 8 7 programm...

Page 439: ...CI and CPU 7 5 SYSCLK 10 21 SYSFAIL assertion 11 8 System bus 6 1 address map of 5 1 address space 5 3 addresses decoding of 6 4 System bus cont d arbitration on 6 4 buffering transactions of 7 3 controller 6 1 6 4 error address register 7 14 interface of 6 4 interface to 7 2 System clock 10 17 10 21 System module installing 2 14 System getting information about 12 5 T Tag enable register 6 16 Ter...

Page 440: ...terrupt vector base register 11 7 register writer read test 4 28 VIC cont d release control register 10 20 write post failure 11 8 VIC64 chip 9 29 byte swapping for 10 27 configuring 10 32 interrupt controller 11 4 interrupt ranking for 11 5 interrupts sources of 11 6 VIP PCI configuration register test 4 4 4 28 VIP register write read test 4 4 4 28 vip_diag command with t 1 4 28 with t 2 4 28 wit...

Page 441: ...IL assertion 11 8 timeout timers 10 21 transfer timers 10 22 VMEbus interrupt vector base registers 10 24 VMEbus interrupter interrupt control register 10 25 11 10 VMEbus master 10 2 VMEbus transfer timeout register 10 22 VME_A16_BASE environment variable 3 7 VME_A24_BASE environment variable 3 7 VME_A24_SIZE environment variable 3 7 VME_A32_BASE environment variable 3 7 VME_A32_SIZE environment v...

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