DDC Total-AceXtreme BU-67301B, Design Manual

Page: 70 / 141

H O S T I N T E R F A C E
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com 1/14
61
Table 10. Synchronous Burst Transfers
Non-Multiplexed or
Multiplexed
32-bit or
16-bit
Sequential
or Random
Register or
Memory
Read or
Write
Timing Diagram
Non-Multiplexed 16 Random Memory or
Register
Write Figure 42
Multiplexed 32 Sequential Memory Read Figure 43
Multiplexed 32 Sequential Memory or
Register
Write Figure 44
Multiplexed 16 Sequential Memory Read Figure 45
Multiplexed 16 Sequential Memory or
Register
Write Figure 46
Multiplexed 32-bit or 16-bit Random Memory or
Register
Read or Write Not Supported
Non-Multiplexed or
Multiplexed
32-bit or 16-bit Sequential or
Random
Register Read Not Supported
Non-Multiplexed or
Multiplexed
32-bit or 16-bit Random Memory or
Register
Read Not Supported
Table 11. Synchronous Timing Parameters
REF DESCRIPTION NOTES
Timing Characteristics
UNITS
MIN TYP MAX
f
CLK
HOST_CLK frequency 0 80 MHz
t
CLK
HOST_CLK cycle time 12.5 ns
t
SS
nDATA_STRB setup time (NOTE) 4
t
SH
nDATA_STRB hold time (NOTE) 0
t
CS
nSELECT setup time (NOTE) 4 ns
t
CH
nSELECT hold time (NOTE) 0 ns
t
AS
CPU_ADDR valid setup time (NOTE) 4 ns
t
AH
CPU_ADDR valid hold time (NOTE) 0 ns
t
MS
MSW_nLSW setup time (NOTE) 4 ns
t
MH
MSW_nLSW hold time (NOTE) 0 ns
t
WAIT-READ
Read cycle latency from nDATA_STRB falling edge to
nDATA_RDY falling edge (6•t
CLK
) +
50
(7•t
CLK
) +
75
ns
t
WAIT-
WRITE
Write cycle latency from nDATA_STRB falling edge to
nDATA_RDY falling edge 4•t
CLK
ns
t
DD
CPU_DATA valid delay (NOTE) 10pF load 8 ns
t
RDD
nDATA_RDY delay (NOTE) 10pF load 2 7 ns
t
OH
CPU_DATA output valid hold time (NOTE) 10pF load 2 ns
t
OHZ
CPU_DATA delay to high-Z (NOTE) 10pF load 8 ns