DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
8
Final
Version: DM9000-DS-F02
June 26, 2002
14
RST
I
Hardware Reset Command, active high to reset the DM9000
6,7,8,9,10,
11,12,13,
89,88,87,
86,85,84,
83,82
SD0~15
I/O
Processor Data Bus bit 0~15
93,94,95,
96,97,98
SA4~9
I
Address Bus 4~9
These pins are used to select the DM9000.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9000 is
selected.
92
CMD
I
Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is ADDRESS port
91
IO16
O
Word Command Indication
When the access of internal memory is word or dword width, this pin will
be asserted
This pin is low active at default
100
INT
O
Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
56,53,52,
51,50,49,
47,46,45,
44,43,41,
40,39,38
37
SD16~31 (in
double word
mode)
I/O
Processor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9000 is set to
double word mode (the straps pin EEDO is pulled high and WAKEUP is
not pull-high)
57
IO32 (in double
word mode)
O
Double Word Command Indication
This pins is used as the double word command indication when the
DM9000 is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohm
internally
5.3 EEPROM Interface
64
EEDI
I
Data from EEPROM
65
EEDO
I/O
Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WAKEUP,
and it can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKEUP EEDO data width
0 0 16-bit
0 1 32-bit
1 0 8-bit
1 1 reserved
