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DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Final

15

Version: DM9000-DS-F02
June 26, 2002

6.7 RX Status Register ( 06H )

Bit

Name

Default

Description

7

RF

0,RO

Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes

6

MF

0,RO

Multicast Frame
It is set to indicate that the received frame has a multicast address

5

LCS

0,RO

Late Collision Seen
It is set to indicate that a late collision is found during the frame reception

4

RWTO

0,RO

Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes

3

PLE

0,RO

Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception

2

AE

0,RO

Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary

1

CE

0,RO

CRC Error
It is set to indicate that the received frame ends with a CRC error

0

FOE

0,RO

FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception

6.8 Receive Overflow Counter Register ( 07H )

Bit

Name

Default

Description

7

RXFU

0,R/C

Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition

6:0

ROC

0,R/C

Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow

6.9 Back Pressure Threshold Register (08H)

Bit

Name

Default

Description

7:4

BPHW

3H, RW

Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)

3:0

JPT

7H, RW

Jam Pattern Time.    Default is 200us
bit3 bit2 bit1 bit0     time
0   0   0   0       5us
0   0   0   1       10us
0   0   1   0       15us
0   0   1   1       25us
0   1   0   0       50us
0   1   0   1      100us
0   1   1   0      150us
0   1   1   1      200us
1   0   0   0      250us
1   0   0   1      300us
1   0   1   0      350us
1   0   1   1      400us
1   1   0   0      450us
1   1   0   1      500us
1   1   1   0      550us
1   1   1   1      600us

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Summary of Contents for DM9000

Page 1: ...internal memory accesses for different processors The PHY of the DM9000 can interface to the UTP3 4 5 in 10Base T and UTP5 in 100Base TX It is fully compliant with the IEEE 802 3u Spec Its auto negotiation function will automatically configure the DM9000 to take the maximum advantage of its abilities The DM9000 also supports IEEE 802 3x full duplex flow control This programming of the DM9000 is ve...

Page 2: ...Purpose Control Register 1EH 18 6 19 General Purpose Register 1FH 18 6 20 TX SRAM Read Pointer Address Register 22H 23H 18 6 21 RX SRAM Write Pointer Address Register 24H 25H 19 6 22 Vendor ID Register 28H 29H 19 6 23 Product ID Register 2AH 2BH 19 6 24 Chip Revision Register 2CH 19 6 25 Special Mode Control Register 2FH 19 6 26 Memory Data Read Command without Address Increment Register F0H 19 6 ...

Page 3: ... Transmit Power Mode 36 10 DC and AC Electrical Characteristics 37 10 1 Absolute Maximum Rating 25 C 37 10 2 Operating Conditions 37 10 3 DC Electrical Characteristics 38 10 4 AC Electrical Characteristics Timing Waveforms 39 10 4 1 TP Interface 39 10 4 2 Oscillator Crystal Timing 39 10 4 3 Processor Register Read Timing 39 10 4 4 Processor Register Write Timing 40 10 4 5 External MII Interface Tr...

Page 4: ...mode flow control IEEE802 3x flow control for full duplex mode Supports wakeup frame link status change and magic packet events for remote wake up Integrated 4K dword SRAM Supports automatically load vendor ID and product ID from EEPROM Supports 4 GPIO pins Optional EEPROM configuration Very low power consumption mode Power reduced mode cable detection Power down mode Selectable TX drivers for 1 1...

Page 5: ... 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 BGRES DGND NC LINK_O WAKEUP PW_RST DGND SD12 IOR 77 78 79 80 81 82 83 84 85 SD15 SD14 SD13 SD8 SD11 SD10 SD9 SA4 DVDD IO16 CMD SA8 SA5 SA6 SA7 SA9 DGND INT IOW AEN IOWAIT DVDD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RST DGND TEST1 TEST2 TEST3 TEST4 DVDD X2_25M X1_25M DGND SD AGND AVDD AVDD RXI RXI AGND AGND TXO TXO AVDD DVDD LINK_I RXD0 RXD1 ...

Page 6: ...3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 BGRES DGND NC LINK_O WAKEUP PW_RST DGND SD12 IOR 77 78 79 80 81 82 83 84 85 SD15 SD14 SD13 SD8 SD11 SD10 SD9 SA4 DVDD IO16 CMD SA8 SA5 SA6 SA7 SA9 DGND INT IOW AEN IOWAIT DVDD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RST DGND TEST1 TEST2 TEST3 TEST4 DVDD X2_25M X1_25M DGND SD AGND AVDD AVDD RXI RXI AGND AGND TXO TXO AVDD DVDD SD31 SD30 SD29 SD28 SD...

Page 7: ...MII Transmit Data 4 bit nibble data outputs synchronous to the TX_CLK when in 10 100Mbps nibble mode TXD 2 0 is also used as the strap pins of IO base address IO base strap pin value of TXD 2 0 10H 300H 54 TX_ EN O External MII Transmit Enable 56 MDIO I O MII Serial Management Data 57 MDC O MII Serial Management Data Clock This pin is also used as the strap pin of the polarity of the INT pin When ...

Page 8: ...p pin MDC See the EEPROM content description for detail 56 53 52 51 50 49 47 46 45 44 43 41 40 39 38 37 SD16 31 in double word mode I O Processor Data Bus bit 16 31 These pins are used as data bus bits 16 31 when the DM9000 is set to double word mode the straps pin EEDO is pulled high and WAKEUP is not pull high 57 IO32 in double word mode O Double Word Command Indication This pins is used as the ...

Page 9: ... 100M S or it is floating for the 10M mode of the internal PHY 61 DUP O Full duplex LED In LED mode 1 Its low output indicates that the internal PHY is operated in full duplex mode or it is floating for the half duplex mode of the internal PHY In LED mode 0 Its low output indicates that the internal PHY is operated in 10M mode or it is floating for the 100M mode of the internal PHY 62 LINK ACT O L...

Page 10: ...l MII device GPIO1 3 defaults are input ports 78 LINK_O O Cable Link Status Output Active High This pin is also used as a strap pin to define whether the MII interface is a reversed MII interface pulled high or a normal MII interface not pulled high This pin has a pulled down resistor about 60k ohm internally 79 WAKEUP O Issue a wake up signal when wake up event happens This pin has a pulled down ...

Page 11: ...DRL EEPROM PHY Low Byte Data Register 0DH XXH EPDRH EEPROM PHY High Byte Data Register 0EH XXH WCR Wake Up Control Register 0FH 00H PAR Physical Address Register 10H 15H Determined by EEPROM MAR Multicast Address Register 16H 1DH XXH GPCR General Purpose Control Register 1EH 01H GPR General Purpose Register 1FH XXH TRPAL TX SRAM Read Pointer Address Low Byte 22H 00H TRPAH TX SRAM Read Pointer Addr...

Page 12: ...terrupt Status Register FEH 00H IMR Interrupt Mask Register FFH 00H Key to Default In the register description that follows the default column takes the form Reset Value Access Type Where Reset Value 1 Bit set to logic one 0 Bit set to logic zero X No default value Access Type RO Read only RW Read Write R C Read and Clear RW C1 Read Write and Cleared by write 1 WO Write only Reserved bits are shad...

Page 13: ... This bit has no meaning when LINKST 0 6 LINKST 0 RO Link Status 0 link failed 1 link OK when Internal PHY is used 5 WAKEST 0 RW C1 Wakeup Event Status Clears by read or write 1 This bit will not be affected after software reset 4 RESERVED 0 RO Reserved 3 TX2END 0 RW C1 TX Packet 2 Complete Status Clears by read or write 1 Transmit completion of packet index 2 2 TX1END 0 RW C1 TX Packet 1 Complete...

Page 14: ...cket index I I Bit Name Default Description 7 TJTO 0 RO Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 LC 0 RO Loss of Carrier It is set to indicate the loss of carrier during the frame transmission It is not valid in internal loopback mode 5 NC 0 RO No Carrier It is set to indicate that there is no carrier signa...

Page 15: ...the received frame ends with a CRC error 0 FOE 0 RO FIFO Overflow Error It is set to indicate that a FIFO overflow error happens during the frame reception 6 8 Receive Overflow Counter Register 07H Bit Name Default Description 7 RXFU 0 R C Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition 6 0 ROC 0 R C Receive Overflow Counter This is a statistic counter to i...

Page 16: ...with time FFFFH 5 TXPEN 0 RW Force TX Pause Packet Enable Enables the pause packet for high low water threshold control 4 BKPA 0 RW Back Pressure Mode This mode is for half duplex mode only It generates a jam pattern when any packet comes and RX SRAM is over BPHW 3 BKPM 0 RW Back Pressure Mode This mode is for half duplex mode only It generates a jam pattern when a packet s DA matches and RX SRAM ...

Page 17: ... up Event This bit will not be affected after software reset 4 SAMPLEEN 0 RW When set it enables Sample Frame Wake up Event This bit will not be affected after software reset 3 MAGICEN 0 RW When set it enables Magic PacketWake up Event This bit will not be affected after software reset 2 LINKST 0 RO When set it indicates that Link Change and Link Status Change Event occurred This bit will not be a...

Page 18: ...he correspondent bit of General Purpose Control Register is 1 the value of the bit is reflected to pin GEPIO3 1 When the correspondent bit of General Purpose Control Register is 0 the value of the bit to be read is reflected from correspondent pins of GEPIO3 1 The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively 0 GEPIO0 1 RW General Purpose When the correspondent bit of General Purpose Con...

Page 19: ...ff time 6 26 Memory Data Read Command without Address Increment Register F0H Bit Name Default Description 7 0 MRCMDX X RO Read data from RX SRAM After the read of this command the read pointer of internal SRAM is unchanged 6 27 Memory Data Read Command with Address Increment Register F2H Bit Name Default Description 7 0 MRCMD X RO Read data from RX SRAM After the read of this command the read poin...

Page 20: ...yte 7 0 TXPLL X R W TX Packet Length Low byte 6 33 Interrupt Status Register FEH Bit Name Default Description 7 6 IOMODE 0 RO Bit 7 Bit 6 0 0 16 bit mode 0 1 32 bit mode 1 0 8 bit mode 1 1 Reserved 5 4 RESERVED 0 RO Reserved 3 ROOS 0 RW C1 Receive Overflow Counter Overflow Latch 2 ROS 0 RW C1 Rx Overflow Latch 1 PTS 0 RW C1 Packet Transmitted Latch 0 PRS 0 RW C1 Packet Received Latch 6 34 Interrup...

Page 21: ... active low when set default active low Bit2 IOW pin is active low when set default active low Bit3 INT pin is active low when set default active high Bit4 INT pin s open collected default force output Bit5 Reserved Bit6 Reserved Bit7 Reserved Bit8 Reserved When word 3 bit 5 4 01 the I O base can be re configured Bit11 09 I O base default 300H 000 300H 001 310H 010 320H 011 330H 100 340H 101 350H ...

Page 22: ...ility LP Next Page LP Ack LP RF Reserved LP FC LP T4 LP TXFDX LP TXHDX LP 10FDX LP 10HDX Link PartnerProtocolSelectorField 06 Auto Neg Expansion Reserved Pardet Fault LPNext PgAble NextPg Able NewPg Rcv LP AutoN Cap 16 Specified Config BP 4B5B BP SCR BP ALIGN BP_AD POK Rsvd TX Rsvd Rsvd Force 100LNK Reserved RPDCTR EN Reset St Mch Pream Supr Sleep mode Remote LoopOut 17 Specified Conf Stat 100 FDX...

Page 23: ... is enabled bit 8 and 13 will be in auto negotiation status 0 11 Power down 0 RW Power Down While in the power down state the PHY should respond to the management transactions During the transition to power down state and while in the power down state the PHY should not generate spurious signals on the MII 1 Power down 0 Normal operation 0 10 Isolate 0 RW Isolate 1 Isolates the PHY from the MII wi...

Page 24: ...mode 0 Not able to perform 100BASE TX in half duplex mode 1 12 10BASE T full duplex 1 RO P 10BASE T Full Duplex Capable 1 Able to perform 10BASE T in full duplex mode 0 Not able to perform 10BASE TX in full duplex mode 1 11 10BASE T half duplex 1 RO P 10BASE T Half Duplex Capable 1 Able to perform 10BASE T in half duplex mode 0 Not able to perform 10BASE T in half duplex mode 1 10 1 7 RESERVED 0 R...

Page 25: ...egisters 1 and 2 work together in a single identifier of the DM9000 The Identifier consists of a concatenation of the Organizationally Unique Identifier OUI a vendor s model number and a model revision number DAVICOM Semiconductor s IEEE assigned OUI is 00606E Bit Bit Name Default Description 2 15 2 0 OUI_MSB 0181H OUI Most Significant Bits Bit 3 to 18 of the OUI 00606E are mapped to bit 15 to 0 o...

Page 26: ...etected 4 12 4 11 RESERVED X RW Reserved Write as 0 ignore on read 4 10 FCS 0 RW Flow Control Support 1 Controller chip supports flow control ability 0 Controller chip doesn t support flow control ability 4 9 T4 0 RO P 100BASE T4 Support 1 100BASE T4 is supported by the local device 0 100BASE T4 is not supported The PHY does not support 100BASE T4 so this bit is permanently set to 0 4 8 TX_FDX 1 R...

Page 27: ...ported by the link partner 0 100BASE T4 is not supported by the link partner 5 8 TX_FDX 0 RO 100BASE TX Full Duplex Support 1 100BASE TX full duplex is supported by the link partner 0 100BASE TX full duplex is not supported by the link partner 5 7 TX_HDX 0 RO 100BASE TX Support 1 100BASE TX half duplex is supported by the link partner 0 100BASE TX half duplex is not supported by the link partner 5...

Page 28: ...ment Function 1 Receive functions descrambler symbol alignment and symbol decoding functions bypassed Transmit functions symbol encoder and scrambler bypassed 0 Normal operation 16 12 BP_ADPOK 0 RW Bypass ADPOK Force signal detector SD active This register is for debug only not release to customers 1 Force SD is OK 0 Normal operation 16 11 RESERVED 0 RO Reserved Write as 0 ignore on read 16 10 TX ...

Page 29: ... Half Duplex Operation Mode After auto negotiation is completed results will be written to this bit If this bit is 1 it means the operation 1 mode is a 100M half duplex mode The software can read bit 15 12 to see which mode is selected after auto negotiation This bit is invalid when it is not in the auto negotiation mode 17 13 10FDX 1 RO 10M Full Duplex Operation Mode After auto negotiation is com...

Page 30: ... 0 Link pulses disabled good link condition forced This bit is valid only in 10Mbps operation 18 13 HBE 1 RW Heartbeat Enable 1 Heartbeat function enabled 0 Heartbeat function disabled When the PHY is configured for full duplex operation this bit will be ignored the collision heartbeat function is invalid in full duplex mode 18 12 SQUELCH 1 RW Squelch Enable 1 normal squelch 0 low squelch 18 11 JA...

Page 31: ...he buffer of the receiving packets So in the write memory operation when the bit 7 of IMR is set the memory address increment will wrap to location 0 if the end of address i e 3K is reached In a similar way in the read memory operation when the bit 7 of IMR is set the memory address increment will wrap to location 0x0C00 if the end of address i e 16K is reached 9 3 Packet Transmission There are tw...

Page 32: ...ssions EMI by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base TX operation By scrambling the data the total energy presented to the cable is randomly distributed over a wide frequency range Without the scrambler energy levels on the cable could peak beyond FCC limitations at frequencies related to the repeated 5B sequences...

Page 33: ... 10010 9 Data 9 1001 10011 A Data A 1010 10110 B Data B 1011 10111 C Data C 1100 11010 D Data D 1101 11011 E Data E 1110 11100 F Data F 1111 11101 I Idle undefined 11111 J SFD 1 0101 11000 K SFD 2 0101 10001 T ESD 1 undefined 01101 R ESD 2 undefined 00111 H Error undefined 00100 V Invalid undefined 00000 V Invalid undefined 00001 V Invalid undefined 00010 V Invalid undefined 00011 V Invalid undefi...

Page 34: ...sely the selection of short or intermediate cable lengths requiring less compensation will cause serious under compensation for longer length cables Therefore the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length 9 6 3 MLT 3 to NRZI Decoder The DM9000 decodes the MLT 3 information from the Digital Adaptive Equalizer i...

Page 35: ...the COL signal on the MII interface Collision detection is disabled in Full Duplex operation 9 9 Carrier Sense Carrier Sense CRS is asserted in half duplex operation during transmission or reception of data During full duplex mode CRS is asserted only during receive operations 9 10 Auto Negotiation The objective of Auto negotiation is to provide a means to exchange information between linked devic...

Page 36: ...ys fast link pules 10Base T normal link pules or 100Base TX MLT3 signals the device will wake up and resume a normal operation mode That can be writing Zero to Reg 16 4 of MII register to disable Power Reduced mode 9 11 1 Power Down Mode The Reg 0 11 of MII register can be set high to enter the Power Down mode which disables all transmit receive functions and MII interface functions except the MDC...

Page 37: ...V Human Body Mode 10 2 Operating Conditions Symbol Parameter Min Max Unit Conditions DVDD AVDD Supply Voltage 3 135 3 465 V 100BASE TX 100 mA 3 3V 10BASE T TX 85 mA 3 3V 10BASE T idle 44 mA 3 3V Auto negotiation 60 mA 3 3V PD Power Dissipation Power Reduced Mode without cable 20 mA 3 3V Power Down Mode 10 mA 3 3V Comments Stresses above which are listed under Absolute Maximum Ratings may cause per...

Page 38: ...uA VIN 0 0V IIH Input High Leakage Current 1 uA VIN 3 3V Outputs VOL Output Low Voltage 0 4 V IOL 4mA VOH Output High Voltage 2 4 V IOH 4mA Receiver VICM RX RX Common Mode Input Voltage 0 9 V 100 Ω Termination Across Transmitter VTD100 100TX Differential Output Voltage 1 9 2 0 2 1 V Peak to Peak VTD10 10TX Differential Output Voltage 4 4 5 5 6 V Peak to Peak ITD100 100TX Differential Output Curren...

Page 39: ...00TX Differential Voltage Overshoot 0 5 10 4 2 Oscillator Crystal Timing Symbol Parameter Min Typ Max Unit Conditions tCKC TCKC 39 998 40 40 002 ns 50ppm tPWH TCKC 16 20 24 ns tPWL OSC Pulse Width Low 16 20 24 ns 10 4 3 Processor Register Read Timing Symbol Parameter Min Typ Max Unit T1 System address valid to IOR valid 5 ns T2 IOR width 22 ns T3 SD Setup time 10 ns T4 IOR invalid to SD invalid 4 ...

Page 40: ...yp Max Unit T1 System Address Valid to IOW Valid 5 ns T2 IOW Width 22 ns T3 SD Setup Time 22 ns T4 SD Hold Time 5 ns T5 IOW Invalid to System Address Invalid 5 ns T6 IOW Invalid to Next IOW validaccess DM9000 84 ns T7 System Address Valid to IO16 IO32 Valid 5 ns T8 System Address Invalid to IO16 IO32 Invalid 5 ns Note 1 The IO16 is valid when the SD bus width is 16 bit or 32 bit and system address...

Page 41: ... Interface Transmit Timing Symbol Parameter Min Typ Max Unit T1 TXEN TXD 3 0 Setup Time 32 ns T2 TXEN TXD 3 0 Hold Time 8 ns 10 4 6 External MII Interface Receive Timing T1 T2 RXCK RXER RXDV RXD 3 0 Symbol Parameter Min Typ Max Unit T1 RXER RXDV RXD 3 0 Setup Time 5 ns T2 RXER RXDV RXD 3 0 Hold Time 5 ns TXCK TXEN TXD 3 0 T1 T2 ...

Page 42: ...M9000 Hold Time 313 ns T4 MDIO by External MII Setup Time 40 ns T5 MDIO by External MII Hold Time 40 ns 10 4 8 EEPROM Interface Timing Symbol Parameter Min Typ Max Unit T1 EECK Frequency 0 375 Mhz T2 EECS Setup Time 500 ns T3 EECS Hold Time 2166 ns T4 EEDO Setup Time 480 ns T5 EEDO Hold Time 2200 ns T6 EEDI Setup Time 80 ns T7 EEDI Hold Time 80 ns T1 T6 T7 EEDI T2 EESS T4 EEDO EECK T5 MDC MDIO dri...

Page 43: ...DM9000 ISA to Ethernet MAC Controller with Integrated 10 100 PHY Final 43 Version DM9000 DS F02 June26 2002 ...

Page 44: ...the transformer to the DM9000 There should be no power or ground planes in the area under the network side of the transformer to include the area under the RJ 45 connector Refer to Figure 4 and 5 Keep chassis ground away from all active signals The RJ 45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor The Band Gap resisto...

Page 45: ...ase T 100Base TX Power Reduction Application Figure 11 2 DM9000 RXI RXI TX TX0 BGGND BGRES Transformer RJ45 3 6 8 1 4 5 2 7 1 1 1 25 1 75 Ω 1 75 Ω 1 75 Ω 1 75Ω 1 3 3V AVCC 0 1µF 0 1µF 0 1µF 0 1µF 0 1µF 2KV or 0 01µF 2KV Chasis GND 8 5KΩ 1 78Ω 1 78Ω 1 50 Ω 1 50 Ω 1 3 3V AVDD AGND AGND AGND AGND 25 26 34 33 30 29 AGND ...

Page 46: ...acitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000 The best placed distance is 3mm from pin The recommended decoupling capacitor is 0 1μF or 0 01μF as required by the design layout 55 DM9000 5 36 20 90 73 72 35 28 27 Figure 11 3 ...

Page 47: ... Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC regulations part 15 Figure 4 shows a recommended ground layout scheme Figure 11 4 ...

Page 48: ...nes should be approximately illustrated in Figure 5 The ferrite bead used should perform an impedance at least 75Ω at 100MHz A suitable bead is the Panasonic surface mound bead part number EXCCL4532U or equivalent A 10μF electrolytic bypass capacitors should be connected between VDD and Ground at the device side of each of the ferrite bead Figure 11 5 ...

Page 49: ...rer Part Number Pulse Engineering PE 68515 H1078 H1012 H1102 Delta LF8200 LF8221x YCL 20PMT04 20PMT05 Halo TG22 3506ND TD22 3506G1 TG22 S010ND TG22 S012ND Nano Pulse Inc NPI 6181 37 NPI 6120 30 NPI 6120 37 NPI 6170 30 Fil Mag PT41715 Bel Fuse S558 5999 01 Valor ST6114 ST6118 Macronics HS2123 HS2213 Table 2 11 8 Crystal Selection Guide A crystal can be used to generate the 25MHz reference clock ins...

Page 50: ...0 at Reverse MII mode pin 87 is pulled high At this application the txclk col and crs pins will be changed from input to output RXCLK TXCLK RXD0 TXD0 RXDV TXEN CRS COL RXER RXD1 RXD2 TXD1 TXD2 MDC MDIO DM9000 Normal MII Reverse MII Link Full Mode Reverse MII Normal MII RXCLK TXCLK RXD0 TXD0 TXEN COL RXER RXD1 RXD2 TXD1 TXD2 MDC MDIO SWITCH HUB TXER TXD3 RXD3 RXDV CRS RXD3 TXD3 ...

Page 51: ...es Dimensions In mm A 0 063 Max 1 60 Max A1 0 004 0 002 0 1 0 05 A2 0 055 0 002 1 40 0 05 b 0 009 0 002 0 22 0 05 c 0 006 0 002 0 15 0 05 D 0 551 0 005 14 00 0 13 E 0 551 0 005 14 00 0 13 e 0 020 BSC 0 50 BSC F 0 481 NOM 12 22 NOM GD 0 606 NOM 15 40 NOM HD 0 630 0 006 16 00 0 15 HE 0 630 0 006 16 00 0 15 L 0 024 0 006 0 60 0 15 L1 0 039 Ref 1 00 Ref y 0 004 Max 0 1 Max θ 0 12 0 12 Notes 1 Dimensio...

Page 52: ...te a jam pattern when any packet coming and RX SRAM over BPHW TableA 1 A After Modification 4 BKPA 0 RW Back pressure mode This mode is for half duplex mode only Generate a jam pattern when any packet coming and RX SRAM over BPHW 3 BKPM 0 RW Back pressure mode This mode is for half duplex mode only Generate a jam pattern when a packet s DA match and RX SRAM over BPHW TableA 1 B Before Modification...

Page 53: ...de Bit 2 1 0 0 normal 0 1 MAC internal loopback 1 0 internal PHY 100M mode digital loopback 1 1 Reserved TableA 3 B Before Modification Symbol Parameter Min Typ Max Unit T3 SD Setup time 5 ns T6 IOW invalid to next IOW access DM9000 80 ns TableA 4 A After Modification Symbol Parameter Min Typ Max Unit T3 SD Setup time 22 ns T6 IOW invalid to next IOW access DM9000 84 ns TableA 4 B ...

Page 54: ...th these unless DAVICOM agrees otherwise in writing Acceptance of the buyer s orders shall be based on these terms Company Overview DAVICOM Semiconductor Inc develops and manufactures integrated circuits for integration into data communication products Our mission is to design and produce IC products that are the industry s best value for Data Audio Video and Internet Intranet applications To achi...

Page 55: ...This datasheet has been downloaded from www DatasheetCatalog com Datasheets for electronic components ...

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