D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
J2 – ODD [1-139]
Pin
Pin Name
Internal Connections
Ball/
pin #
Supply
Group
Type
Voltage
Note
a voltage divider circuit via 5K6 /10K
resistor, thus providing the 3V3
logical voltage output. Please refer to
6.4.1.
J2.99
SPI3_SCLKGP3_15
CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTX
D[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_
SCLK/GP3[15]
AC26
I/O
1.8V/3.3V
J2.101 3.3V
+3V3
-
S
J2.103 DGND
DGND
-
G
J2.105 JTAG_TDI
CPU.TDI
Y7
I
1.8V/3.3V
J2.107 JTAG_TMS
CPU.TMS
AA7
I/O
1.8V/3.3V
J2.109 PORSTn
CPU.PORn
F1
I
1.8V/3.3V
J2.111 SPI3_SCS1n/GP3_14
CPU.VOUT[1]_R_CR[4]/EMAC[1]_MTX
D[3]/VIN[1]A_D[15]/SPI[3]_SCS[1]n/G
P3[14]
AG27
I/O
J2.113 SPI3_D1/UART3_RTSn/GP2_
29
CPU.VOUT[1]_HSYNC/EMAC[1]_MCOL/
VIN[1]A_VSYNC/PATA_HDDIR/SPI[3]_D[
1]/UART3_RTSn/GP2[29
AC24
I/O
J2.115 EMAC0_PHY_LED_LINK/ACT
LAN.LED1
3
J2.117 EMAC0_PHY_LED_SPEED
LAN.LED2
2
J2.119 SPI3_D0/UART3_CTSn/GP2_
30
CPU.VOUT[1]_VSYNC/EMAC[1]_MCRS/
VIN[1]A_FLD/VIN[1]A_DE/SPI[3]_D[0]/
UART3_CTSn/GP2[30]
AA23
I/O
J2.121 UART3_TXD/SD1_SDWP
CPU.UART0_DSRn/UART3_TXD/SPI[0]_
SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[
3]
AG4
I/O
1.8V/3.3V
J2.123 UART3_RTSn
CPU.UART0_RIN/UART3_RTSn/UART1_
RXD/GP1[5]
AF4
I/O
1.8V/3.3V
J2.125 VIN1A_D3/GP3_3
CPU.VOUT[1]_B_CB_C[6]/EMAC[1]_MR
XD[2]/VIN[1]A_D[3]/UART3_RXD/GP3[
3]
AD25
I/O
1.8V/3.3V
J2.127 ETH_CTTD
-
-
J2.129 ETH_TX-
LAN.TXN
28
J2.131
LAN.TXP
29
J2.133
LAN.RXP
31
J2.135 ETH_RX-
LAN.RXN
30
J2.137 ETH_CTRD
-
-
August, 2014
41/78
