DAT 6000
17
PRELIMINARY
EXAMPLE n°2 : 2 or 4 channels with synchronism control
The continuous control of the received bit allow a sure synchronization of the
procedure. When the synchronism is lost, the next reading will be surely correct
because it will starts only when a synchronism bit will be recognized. It is not
necessary to use the ENABLE signal.
START
ENABLE HIGH
DELAY
n = n - 1
n = 0 ?
READ BIT
SYNC
?
REGISTER [n] = y
CHANNEL (a) =
REGISTER
n = 15
a = a + 1
Definitions:
ENABLE, CLK and DATA = interface signals
SYNC = synchronism bit
REGISTER = data reading buffer
n = a bit of REGISTER buffer (0..15)
CHANNEL = digital channel measurement value
a = channel number (1,2,3 or 4)
x, y = bits
DELAY = delay function (ms). The delay time must be
higher than the setting of the digital filter
DELAY
CLK LOW
DELAY
x = DATA
y = DATA
CLK HIGH
x & y
compare
SYNC
ERROR
READ BIT
a = 0
end of channels reading
YES
NO
YES
NO
NO
YES
read next channel
end of channel reading
read next bit
read input bit
READ BIT
DATA
?
YES
NO
data-bit received
wrong bit received
DATA
x=1
y=0
x=0
y=1
x=y
the first bit is the
most significant
synchronism found
first channel reading
ENABLE LOW
DELAY
a = 2 ?
(NOTE 1)
NOTE 2
A
NOTE 1 : to be modified following the number of channels to be read ( write " a = 4 ? " for the 4 channels reading )
NOTE 2 : follow the (A) option to reset the device or for not reading the unused channels
