Dlrcet Memory
Access
Eight
DMA
channels are supported
by
the system.
Two Intel
8237—5
DMA
controller
chips
(four
channels
in
each
chip)
are used
to provide eight
DMA
channels.
The
DMA
channels are assigned
as
follows:
CTR
1
CTR 2
CH 0
Spare
CH 4
Cascade
for CTRL
1
CH
1
SDLC
CH 5
Spare
CH 2
Diskette
CH 6
Spare
CH 3
Spare
CH 7
Spare
DMA
Channel
Channels
0
through 3
are contained
in DMA
controller
1.
Transfers
of
8-bit
data,
8-bit l/O
adapters and
8-bit
or
16—bit
system
memory
are supported
by
these
channels. Each
of
these
channels
will
transfer
in
64KB
blocks
throughout the
16—megabyte
system address
space.
Channels
4 through 7
are contained
in DMA
controller
2. To
cascade channels
0
through
3
to
the
microprocessor,
use
channel
4.
Transfers
of
16—bit
data
between
16—bit
adapters
and
16-bit
system
memory
are supported
by
channels
5, 6
and
7. DMA
channels
5 through 7
will
transfer data
in
128KB
blocks throughout
the
16—megabyte
system address
space. These channels
will
not
transfer data
on odd-
byte
boundaries.
1
)
)
O
The
addresses forthe page register are as
follows:
Page Register
l/O
Hex
Address
DMA
Channel
0
0087
DMA
Channel
1
0083
DMA
Channel
2
0081
DMA
Channel
3
0082
DMA
Channel
5
0088
DMA
Channel
6
0089
DMA
Channel 7
008A
Refresh
008F
Address generation
for
the
DMA
channels
is
as
fol-
lows:
For
DMA
Channels
3
through
0
Source
DMA
Page
Registers
8237A
-
5
Address
A23
<=>
A16
A15
<=>
A0
NOTE:
To
generate the addressing
signal “byte high
enable" (BHE), invert
address
line A0.
For
DM'A
Channels
7
through 5
Source
DMA
Page
Registers
8237A
-
5
Address
A23
<2:>
A17
A16
<:>
A1
NOTE: The BHE
and
A0
addressing signals are
forced to
a
logical
0. DMA
channel
addresses
do not
increase
or
decrease
through
page boundaries
64KB
for
channels
0
through 3
and
128KB for
channels
5
through
7.
37
Summary of Contents for Mini 80386SX
Page 1: ...o Mini 803863X 20MHz Mainboard User s Manual ...
Page 26: ......