Data Translation DT9840 Series, User Manual

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Register Description
57
On the DT9841, DT9841E, and DT9841-VIB, once the A/Ds are started, the serial data is
packed as 32 bits in the Spartan chip. The data is left-hand justified (the right 8 bits are filled
with zeros) and the data encoding is twos complement.
On the DT9842/2 and DT9842/8, once the A/Ds are started, the data is packed as 32 bits in
the Spartan chip and the data is left-hand justified (the right 16 bits are filled with zeros, the
data encoding is twos complement).
Interrupt EXT_INT6 is asserted to the DSP chip when the conversion is completed (A/D
Done) and the data is ready (INT6 = pin D2). This interrupt initiates a DMA transfer on DMA
channel 6. The acquired data is stored in the input FIFO and either sent to the DSP for further
processing or to host memory over the USB bus. All samples must be read before the next
A/D Done.
An orderly stop is done when the DSP firmware stops sending data to the host, but leaves the
A/D running, discarding new data. This allows the module to transfer the last sample to the
host or memory and restart data collection without performing another calibration.
The A/D error bit (bit 27 of the Hardware Control and Status register, described in Table 5 on
page 47 ) is set if the A/D clock is set faster than the A/D converter specification or if the data
was not read fast enough by the DSP or host. This error must be cleared by the DSP or host.
Table 9 describes the DMA address map.
Table 9: DMA Address Map
Address Register Description Type
0xB0004000 A/D Data 0 above physical memory, read only R
0xB0004004 A/D Data 1 R
0xB0004008 A/D Data 2
a
a. Ignore the data in this register for DT9841E modules.
R
0xB000400C A/D Data 3
a
R
0xB0004010 A/D Data 4
a
R
0xB0004014 A/D Data 5
a
R
0xB0004018 A/D Data 6
a
R
0xB000401C A/D Data 7
a
R
0xB0004020 Flag Bits, Digital Port 2
b
,Digital Port 1, Digital Port 0
c
b. For the DT9841-VIB module, bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is
used as the SDA data output; the remaining bits (2-7) of digital port 2 are reserved. See page 51 for
more information.
c. Note that the digital ports are located at address 0xB0004020 along with the flag bits. This allows a
single burst through the sequential addresses to acquire all the input data and flags. (Active state = 1).
All reads are done at the 40.0 ns clock rate using the CE3 setup. Refer to
Table 10 for more information
on the flag bits. Refer to Table 15 on page 70 for more information on CE3.
R
0xB0004024 Counter Timer 0 R
0xB0004028 Counter Timer 1 R
0xB000402C Counter Timer 2 R