Data Translation DT3155, User Manual

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Principles of Operation
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After it has been adjusted, the DT3155 board digitizes the video
signal between the adjusted minimum full-scale voltage and the
white level voltage.
Note: For proper operation, it is recommended that you do not use
a white level value below 502 mV. In addition, the difference
between the maximum full-scale voltage and the adjusted minimum
full-scale voltage (0 V) should not be less than 500 mV.
Pixel Clock
The DT3155 generates a 12.5 MHz pixel clock signal for 60 Hz image
formats and a 15 MHz pixel clock signal for 50 Hz image formats.
Using the Digital Clock Sync Circuitry, which has no more than
±5.0 ns jitter, the DT3155 board synchronizes the pixel clock to the
first frame of an asynchronous external video source.
External Trigger
The DT3155 frame grabber provides pin 4 (EXT_TRIG_IN) on
connector J1 for connecting an external trigger input.
Using an external trigger, you can synchronize an acquisition with an
external event. You can enable and invert the external trigger using
software. When the external trigger is enabled, image acquisition
starts when a low-to-high edge (rising-edge) transition occurs or if
the external trigger is inverted, when a high-to-low (falling-edge)
transition occurs on pin 4 of connector J1.