Data Translation DT300 Series, User Manual

Page: 72 / 164

Chapter 6
72
This chapter describes the analog input, analog output, digital I/O, and counter/timer
features of the DT300 Series board. To frame the discussions, refer to the block diagram shown
in
Figure 24 . Note that bold entries indicate signals you can access.
Figure 24: Block Diagram of the DT300 Series Boards
Trigger/Clock
Logic
A/D Counter,
24-bits
TScan Counter
24-bit
Ext A/D Clock
Ext TTL Trig
20 MHz Clock
A/D Clk
Analog In
16 Channel Mux
Ch. Sel
Gain Amp
(1, 2, 4, 8)
ADC
Tristate
1 kSample
Input FIFO
PCI Bus Interface
PCI Bus
Gain Sel
A/D Clk
DIO Ports A
and B
Input Sel
Ch. Sel
1 K Entry
CGL FIFO
CGL Reg.
Channel
Parameter
Reg.
Gain Sel
Input Sel
Bidirectional
8-bit Latch
Bidirectional
8-bit Latch
20 MHz
Clock
DIO Port B
[7:0]
DIO Port A
[7:0]
User Clk [3:0]
User Gate [3:0]
User Out [3:0]
4 User
Counter/
Timers,
16-bit ea.
Discard
sample
Multiplying
DAC*
Multiplying
DAC*
Analog
Output 1
Analog
Output 0
DIO Port C [6:0]
*DACs not included on DT301,
DT303, or DT321 boards.
SW_Clk1
SW_Clk0
Ser_Dat
Ser_Clk