Data Translation DT300 Series, User Manual

Page: 160 / 164

Index
160
formatting data
analog input 86
analog output 90
frequency
base clock 115
external A/D sample clock 77
external C/T clock 95
internal A/D clock 115
internal A/D sample clock 76
,
115
internal C/T clock 95
,
115
internal retrigger clock 79
,
110
frequency measurement 99
G
gain
actual available 111
analog input 75
analog output 89
number of 111
programmable 111
gain, analog input 76
gate input signal 94
,
96
gate type 96
falling edge 96
high level 96
high-edge 116
high-level 116
internal 116
low-edge 116
low-level 96
,
116
none (software) 96
rising edge 96
generating continuous pulses 101
H
help 125
help, online 61
HES14-21 power supply 19
high-edge gate type 96
,
116
high-level gate type 96
,
116
high-to-low pulse output 97
Host Block Overflow error 88
I
inhibiting values from a channel 74
inprocess buffers 110
input configuration
differential analog 47
pseudo-differential analog 47
single-ended analog 47
Input FIFO Overflow error 88
input ranges 75
inserting the board 28
internal clock 115
A/D sample 76
C/T 95
internal gate type 96
,
116
internal retrigger clock 79
J
J1 connector pin assignments
DT300 Series board 142
STP300 screw terminal panel 144
STP68 panel 147
J2 connector pin assignments
STP300 screw terminal panel 146
jumper W1 35
jumpers W4 to W7 35
L
LabVIEW 18
level gate type
high 96
low 96
loading the device driver
Windows 7 30
Windows Vista 29
Windows XP 29
low-edge gate type 96
,
116
low-level gate type 96
,
116
low-to-high pulse output 97
LV-Link 18
M
MaxDifferentialChannels 111
MaxExtClockDivider 115
MaxFrequency 115
MaxMultiScanCount 110
MaxRetriggerFreq 110
MaxSingleEndedChannels 111
Measure Foundry 18
measuring frequency 99
MinExtClockDivider 115
MinFrequency 115
MinRetriggerFreq 110