ADP-SDI01 User’s Manual(Rev(1.1)
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8-
http://www.daqsystem.com
2.4 SW2 Setting
ON
1 2 3 4
T
IM
8
6
1
A
N
C
_
B
L
A
N
K
2
0
B
IT
/1
0
B
IT
D
V
B
/A
S
I
[Figure 2-5. SW2 switch]
TIM861
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to select the external CEA-861 timing mode.
DETECT_TRS : 0, TIM861 : 0
the device extracts all internal timing from
the supplied H:V:F(Hsync:VSync:Frame) timing signals.
DETECT_TRS : 0, TIM861 : 1
the device extracts all internal timing from
the supplied H:V:F(Hsync:VSync:DE) timing signals.
DETECT_TRS : 1
the device extracts all internal timing from TRS signals
embedded in the supplied video stream.
ANC_BLANK
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
When ANC_BLANK is LOW, the Luma and Chroma input data is set to the
appropriate blanking levels during the H and V blanking intervals.
When ANC_BLANK is HIGH, the Luma and Chroma data pass through the
device unaltered.
Only applicable in SMPTE mode.
20BIT/10BIT
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to select the Input Bus width.
DVB_ASI
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to enable/disable DVB-ASI data transfer.
DVB_ASI : 1, SMPTE_BYPASS : 0
the device will carry out DVB-ASI
word alignment, I/O processing and transmission.
DVB_ASI : 0, SMPTE_BYPASS : 0
the device operates in data-through mode.