ADP-SDI01 User’s Manual(Rev(1.1)
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7-
http://www.daqsystem.com
2.3 SW1 Setting
ON
1 2 3 4
S
D
O
_
E
N
/D
IS
R
A
T
E
_
S
E
L
0
R
A
T
E
_
S
E
L
1
D
E
T
E
C
T
_
T
R
5
[Figure 2-4. SW1 switch]
SDO_EN/DIS
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to enable/disable the Serial Digital Output Stage.
When SDO_EN/DIS is LOW, the serial digital output signals SDO and SDO
are disabled and become high impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and SDO
are enabled.
RATE_SEL1..0
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to configure the operating data rate.
RATE_SEL0 RATE_SEL1 Data Rate
0 0 1.485 or 1.485/1.00GB/s
0 1 2.97 or 2.97/1.00GB/s
1 0 270Mb/s
DETECT_TRS
--- Control Signal Input/
Signal levels are LVCMOS / LVTTL compatible
It is used to select external HVF or TRS extracting timing mode.
When DETECT_TRS is LOW, the device extracts all internal timing from
the supplied H:V:F or CEA-861 timing signals, depending on the status of
the TIM861 pin.
When DETECT_TRS is LOW, the device extracts all internal timing from
the TRS signals embedded in supplied video stream.