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DS2154

071498 66/71

RECEIVE SYSTEM SIDE AC TIMING Figure 14–5

RSER/RSIG

RCHCLK

RCHBLK

RSYNC

MSB

RSYSCLK

OF CHANNEL 1

RMSYNC

NOTES:

1. RSYNC is in the output mode (RCR1.5=0).

2. RSYNC is in the input mode (RCR1.5=1).

RECEIVE LINE INTERFACE AC TIMING Figure 14–6

RCLKI

RPOSI, RNEGI

RCLKO

RPOSO, RNEGO

Summary of Contents for DS2154

Page 1: ...KAGE OUTLINE 100 1 ORDERING INFORMATION DS2154L 0 C to 70 C DS2154LN 40 C to 85 C DESCRIPTION The DS2154 Enhanced Single Chip Transceiver ESCT contains all of the necessary functions for con nection t...

Page 2: ...Alarm Criteria 5 0 ERROR COUNT REGISTERS BPV or Code Violation Counter CRC4 Error Counter E bit Counter FAS Error Counter 6 0 DSO MONITORING FUNCTION 7 0 SIGNALING OPERATION Processor Based Signaling...

Page 3: ...Clock and Data Recovery Transmit Waveshaping and Line Driving Jitter Attenuator 13 0 TIMING DIAGRAMS Synchronization Flowchart Transmit Data Flow Diagram 14 0 CHARACTERISTICS Absolute Maximum Ratings...

Page 4: ...RCL RLOS RRA and RAIS alarms now interrupt on change of state 4 8 192 MHz clock synthesizer 1 Per channel loopback 8 Addition of hardware pins to indicate carrier loss and signaling freeze 1 Line int...

Page 5: ...IT INSERTION SA INSERTION PER CHANNEL LOOPBACK SIGNALING INSERTION CRC4 GENERAITON HDB3 ENCODE AIS GENERAITON PER CHANNEL CODE INSERT SA AND SI EXTRACTION SIGNALING EXTRACTION E BIT COUNTER FAS ERROR...

Page 6: ...necessary The transmitformatter will provide the necessary frame mul tiframe data overhead for E1 transmission Once the data stream has been prepared for transmission it is sent via the jitter attenua...

Page 7: ...23 NC No Connect 24 RVSS Receive Analog Signal Ground 25 INT O Interrupt 26 NC No Connect 27 NC No Connect 28 NC No Connect 29 TTIP O Transmit Analog Tip Output 30 TVSS Transmit Analog Signal Ground...

Page 8: ...ata Bus Bit 2 Address Data Bus Bit 2 59 D3 AD3 I O Data Bus Bit 3 Address Data Bus Bit 3 60 DVSS Digital Signal Ground 61 DVDD Digital Positive Supply 62 D4 AD4 I O Data Bus Bit 4 Address Data Bus Bit...

Page 9: ...IPTION Table 1 2 TRANSMIT SIDE DIGITAL PINS Transmit Clock TCLK A 2 048 MHz primary clock Used to clock data through the transmit side formatter Must be present for the parallel control port to operat...

Page 10: ...transmit side elastic store is enabled See Section 13 for timing examples Transmit Elastic Store Data Output TESO Updated on the rising edge of TCLK with data out of the the transmit side elastic sto...

Page 11: ...LK 1 544 MHz or 2 048 MHz clock Only used when the elastic store function is enabled Should be tied low in applications thatdo not use the elastic store Can be burst at rates up to 8 192 MHz Receive S...

Page 12: ...address bit In multiplexed bus operation MUX 1 serves to demultiplex the bus on a positive going edge Write Input WR Read Write R W WR is an active low signal LINE INTERFACE PINS Master Clock Input MC...

Page 13: ...R BPV or Code Violation Count 1 VCR1 01 R BPV or Code Violation Count 2 VCR2 02 R CRC4 Error Count 1 FAS Error Count 1 CRCCR1 03 R CRC4 Error Count 2 CRCCR2 04 R E Bit Count 1 FAS Error Count 2 EBCR1...

Page 14: ...TCBR4 26 R W Transmit Idle 1 TIR1 27 R W Transmit Idle 2 TIR2 28 R W Transmit Idle 3 TIR3 29 R W Transmit Idle 4 TIR4 2A R W Transmit Idle Definition TIDR 2B R W Receive Channel Blocking 1 RCBR1 2C R...

Page 15: ...Transmit Signaling 9 TS9 48 R W Transmit Signaling 10 TS10 4A R W Transmit Signaling 11 TS11 4B R W Transmit Signaling 12 TS12 4C R W Transmit Signaling 13 TS13 4D R W Transmit Signaling 14 TS14 4E R...

Page 16: ...C9 69 R W Transmit Channel 10 TC10 6A R W Transmit Channel 11 TC11 6B R W Transmit Channel 12 TC12 6C R W Transmit Channel 13 TC13 6D R W Transmit Channel 14 TC14 6E R W Transmit Channel 15 TC15 6F R...

Page 17: ...e Channel 10 RC10 8A R W Receive Channel 11 RC11 8B R W Receive Channel 12 RC12 8C R W Receive Channel 13 RC13 8D R W Receive Channel 14 RC14 8E R W Receive Channel 15 RC15 8F R W Receive Channel 16 R...

Page 18: ...tied high Motorola timing will be selected All Motorola bus signals are listed in parenthesis See the timing diagrams in the A C Electrical Characteris tics in Section 14 for more details 3 0 CONTROL...

Page 19: ...mode RCR1 6 1 0 RSYNC outputs CAS multiframe boundaries 1 RSYNC outputs CRC4 multiframe boundaries RSM RCR1 6 RSYNC Mode Select 0 frame mode see the timing in Section 13 1 multiframe mode see the timi...

Page 20: ...tion set to zero to force RLCLK low during Sa8 bit position See Section 13 for tim ing details Sa7S RCR2 6 Sa7 Bit Select Set to one to have RLCLK pulse at the Sa7 bit position set to zero to force RL...

Page 21: ...m TS0 to TS15 registers TUA1 TCR1 4 Transmit Unframed All Ones 0 transmit data normally 1 transmit an unframed all one s code at TPOSO and TNEGO TSiS TCR1 3 Transmit International Bit Select 0 sample...

Page 22: ...set to zero to not source the Sa4 bit See Section 13 for timing details ODM TCR2 2 Output Data Mode 0 pulses at TPOSO and TNEGO are one full TCLKO period wide 1 pulses at TPOSO and TNEGO are 1 2 TCLK...

Page 23: ...TCMC RFF RFE SYMBOL POSITION NAME AND DESCRIPTION ECUS CCR2 7 Error Counter Update Select See Section 5 for details 0 update error counters once a second 1 update error counters every 62 5 ms 500 fram...

Page 24: ...e is bypassed 1 elastic store is enabled TCBFS CCR3 6 Transmit Channel Blocking Registers TCBR Function Select 0 TCBRs define the operation of the TCHBLK output pin 1 TCBRs define which signaling bits...

Page 25: ...CR4 5 Line Interface AIS Generation Enable See Figure 1 1 for details 0 allow normal data from TPOSI TNEGI to be transmitted at TTIP and TRING 1 force unframed all ones to be transmitted at TTIP and T...

Page 26: ...s precede a read of the SR1 SR2 and RIR registers with a write The byte written to the register will inform the DS2154 which bits the user wishes to read and have cleared The user will write a byte to...

Page 27: ...Store Empty Set when the transmit side elastic store buffer empties and a frame is repeated JALT RIR 5 JitterAttenuatorLimitTrip SetwhenthejitterattenuatorFIFOreachesto within 4 bits of its limit use...

Page 28: ...naling All Ones Signaling Change Set when the contents of timeslot 16 contains less than three zeros over 16 consecutive frames This alarm is not disabled in the CCS signaling mode Both RSA1 and RSA0...

Page 29: ...7 Hex MSB LSB RMF RAF TMF SEC TAF LOTC RCMF TSLIP SYMBOL POSITION NAME AND DESCRIPTION RMF SR2 7 Receive CAS Multiframe Set every 2 ms regardless if CAS signaling is enabled or not on receive multifra...

Page 30: ...interrupt masked 1 interrupt enabled RUA1 IMR1 3 Receive Unframed All Ones 0 interrupt masked 1 interrupt enabled RRA IMR1 2 Receive Remote Alarm 0 interrupt masked 1 interrupt enabled RCL IMR1 1 Rec...

Page 31: ...ion Count Register 1 VCR1 is the most signifi cant word and VCR2 is the least significant word of a 16 bit counter that records either BiPolar Violations BPVs or Code Violations CVs If CCR2 6 0 then t...

Page 32: ...bits of the 12 bit FAS error counter 5 3 E Bit Counter E bit Count Register 1 EBCR1 is the most significant word and EBCR2 is the least significant word of a 10 bit counter that records Far End Block...

Page 33: ...ill determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register In the receive direction the RCM0 to RCM4 bits in the CCR5 register need to be properly se...

Page 34: ...smit DS0 Channel Bit 2 B8 TDS0M 0 Transmit DS0 Channel Bit 1 LSB of the DS0 channel last bit to be transmitted CCR5 COMMON CONTROL REGISTER 5 Address AA Hex repeated here from section 3 for convenienc...

Page 35: ...cessary The processor based signaling is covered in Section 7 1 and the hardware based signaling is covered in Section 7 2 7 1 PROCESSOR BASED SIGNALING The Channel Associated Signaling CAS bits embed...

Page 36: ...e boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 SR2 7 to know when to retrieve the signaling bits The user has a full 2 ms to retrieve the signal...

Page 37: ...to update the signaling bits The bit will be set every 2 ms and the user has 2 ms to update the TSR s before the old data will be retransmitted ITU specifications recommend that the ABCD signaling not...

Page 38: ...ng action as if a loss of synchronization carrier loss or slip has occurred The RSIGF output pin provides a hard ware indication that a freeze is in effect The RSIGF pin will go high immediately upon...

Page 39: ...he E1 line to the backplane and is covered in Section 8 2 8 1 TRANSMIT SIDE CODE GENERATION In the transmit direction there are two methods by which channel data from the backplane can be overwritten...

Page 40: ...LSB TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0 SYMBOL POSITION NAME AND DESCRIPTION TIDR7 TIDR 7 MSB of the Idle Code this bit is transmitted first TIDR0 TIDR 0 LSB of the Idle Code this bit is...

Page 41: ...e placed in the Receive Channel Registers RC1 to RC32 RC1 TO RC32 RECEIVE CHANNEL REGISTERS Address 80 to 9F Hex for brevity only channel one is shown see Table 1 3 for other register address MSB LSB...

Page 42: ...BR3 RCBR4 RECEIVE CHANNEL BLOCKING REGISTERS Address 2B to 2E Hex MSB LSB CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH32 CH31 CH30...

Page 43: ...sync at the RSYNC pin RCR1 5 1 or having the RSYNC pin provide a pulse on frame mul tiframe boundaries RCR1 5 0 If the user wishes to obtain pulses at the frame boundary then RCR1 6 must be set to zer...

Page 44: ...ar ing of the TCR1 3 bit Please see the timing diagrams and the transmit data flow diagram in Section 13 for examples 11 2 INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME On the receive side the RAF an...

Page 45: ...mmed with the seven bit FAS word the DS2154 does not automatically set these bits SYMBOL POSITION NAME AND DESCRIPTION Si TAF 7 International Bit 0 TAF 6 Frame Alignment Signal Bit 0 TAF 5 Frame Align...

Page 46: ...rieve the data before it is lost The MSB of each register is the first received Please see the register descriptions below and the Transmit Data Flow diagram in Section 13 for more details On the tran...

Page 47: ...me TSaCR TRANSMIT Sa BIT CONTROL REGISTER Address 1C Hex MSB LSB SiAF SiNAF RA Sa4 Sa5 Sa6 Sa7 Sa8 SYMBOL POSITION NAME AND DESCRIPTION SiAF TSaCR 7 International Bit in Align Frame Insertion Control...

Page 48: ...le 12 2 L0 LICR 5 Line Build Out Bit 0 Transmit waveshape setting see Table 12 2 EGL LICR 4 Receive Equalizer Gain Limit 0 12 dB 1 43 dB JAS LICR 3 Jitter Attenuator Select 0 place the jitter attenuat...

Page 49: ...TION TRANSFORMER RETURN LOSS RT SEE FIGURE 12 1 000 75 ohm normal See Note 1 1 1 15 step up NM 0 ohms 001 120 ohm normal 1 1 15 step up NM 0 ohms 010 75 ohm w protection resistors 1 1 15 step up NM 8...

Page 50: ...e a gapped bursty clock at the TCLKI pin if the jit ter attenuator is placed on the transmit side If the incoming jitter exceeds either 120 UIpp buffer depth is 128 bits or 28 UIpp buffer depth is 32...

Page 51: ...10 1 0 1 MINIMUM TOLERANCE LEVEL AS PER ITU G 823 DS2154 TRANSMIT WAVEFORM TEMPLATE Figure 12 3 0 0 1 0 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 0 S C A L E D A M P LIT U D E 50 100 150 200 2...

Page 52: ...4 JITTER ATTENUATION Figure 12 4 FREQUENCY Hz 0 dB 20 dB 40 dB 60 dB 1 10 100 1K 10K J I T T E R A T T E N U A T IO N d B 100K ETS 300 011 AND TBR12 PROHIBITED AREA 40 ITU G 7XX PROHIBITED AREA DS2154...

Page 53: ...s well as the rest of the receive data stream 5 This diagram assumes the CAS MF begins with the FAS word RECEIVE SIDE BOUNDARY TIMING WITH ELASTIC STORE DISABLED Figure 13 2 RCLK RSYNC RFSYNC RCHCLK R...

Page 54: ...d forced to one 2 RSYNC is in the output mode RCR1 5 0 3 RSYNC is in the input mode RCR1 5 1 4 RCHBLK is programmed to block Channel 24 RECEIVE SIDE 2 048 MHz BOUNDARY TIMING WITH ELASTIC STORE ENABLE...

Page 55: ...E BOUNDARY TIMING Figure 13 6 TCLK TSER TSYNC1 TFSYNC TSYNC2 TCHCLK CHANNEL 2 CHANNEL 1 TCHBLK3 TLCLK4 TLINK4 Don t Care LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB MSB LSB Don t Care TSIG B CHANNEL 2 CHANNEL...

Page 56: ...B LSB CHANNEL 24 F BIT NOTES 1 TCHBLK is programmed to block Channel 23 2 The F bit position is ignored by the DS2154 TRANSMIT SIDE 2 048 MHz WITH ELASTIC STORE ENABLED Figure 13 8 TSYSCLK TSER TSSYNC...

Page 57: ...20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK1 LSB MSB TIMESLOT 25 TIMESLOT 26 RCLK RSYSCLK RSER TSER RCHCLK TCHCLK RCHBLK TCHCLK DETAIL TCLK TSYSCLK NOTE 1 RC...

Page 58: ...NT CRC4 SYNC COUNTER CRC4SA 0 8 MS TIME OUT CRC4 MULTIFRAME SEARCH IF ENABLED VIA CCR 1 0 CRC4SA 1 CRC4 SYNC CRITERIA MET CRC4SA 0 RESET CRC4 SYNC COUNTER SET FASRC RIR 1 FAS RESYNC CRITERIA MET CHECK...

Page 59: ...NSERTION CONTROL VIA TIR1 2 3 4 TCBR1 2 3 4 TCR1 5 CCR3 6 CRC4 MULTIFRAME ALIGNMENT WORD GENERATION CCR1 4 E BIT GENERATION TCR2 1 AUTO REMOTE ALARM GENERATION CCR2 4 0 RECEIVE SIDE CRC4 ERROR DETECTO...

Page 60: ...bility RECOMMENDED DC OPERATING CONDITIONS 0 C to 70 C for DS2154L 40 C to 85 C for DS2154LN PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 VIH 2 0 VDD 0 3 V Logic 0 VIL 0 3 0 8 V Supply VDD 4 75 5...

Page 61: ...me tRWH 10 ns R W Set Up time before DS high tRWS 50 ns CS Set Up time before DS WR or RD active tCS 20 ns CS Hold time tCH 0 ns Read Data Hold time tDHR 10 50 ns Write Data Hold time tDHW 0 ns Muxed...

Page 62: ...et Up to RSYSCLK Falling tSU 20 tSH 5 ns RSYNC Pulse Width tPW 50 ns RPOSI RNEGI Set Up to RCLKI Falling tSU 20 ns RPOSI RNEGI Hold From RCLKI Falling tHD 20 ns RSYSCLK RCLKI Rise and Fall Times tR tF...

Page 63: ...READ AC TIMING BTS 0 MUX 1 Figure 14 1 ALE WR RD CS AD0 AD7 tCYC PWASH PWEH tASD tASED tASL tDDR tCH tDHR tASD tCS tAHL PWEL INTEL BUS WRITE AC TIMING BTS 0 MUX 1 Figure 14 2 ALE WR RD CS AD0 AD7 PWA...

Page 64: ...W tAHL tASL tASED PWEH RECEIVE SIDE AC TIMING Figure 14 4 RCLK RSER RDATA RSIG RCHCLK RCHBLK RFSYNC RMSYNC RSYNC1 RLCLK2 RLINK tD1 tD2 tD2 tD2 tD2 tD2 tD1 MSB OF CHANNEL 1 Sa4 TO Sa8 BIT POSITION NOTE...

Page 65: ...or TSSYNC Set Up to TCLK or TSYSCLK falling tSU 20 tCH 5 or tSH 5 ns TSYNC or TSSYNC Pulse Width tPW 50 ns TSER TSIG TDATA TLINK TPOSI TNEGI Set Up to TCLK TSYSCLK TCLKI Falling tSU 20 ns TSER TSIG T...

Page 66: ...RSYNC2 tSU tPW tD4 tD4 tD3 MSB RSYSCLK tR tF tSL tSH tSP OF CHANNEL 1 tD4 RMSYNC tD4 NOTES 1 RSYNC is in the output mode RCR1 5 0 2 RSYNC is in the input mode RCR1 5 1 RECEIVE LINE INTERFACE AC TIMIN...

Page 67: ...1 TSYNC is in the output mode TCR1 0 1 2 TSYNC is in the input mode TCR1 0 0 3 TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled 4 TCHCLK and TCHBLK are sync...

Page 68: ...K TSSYNC NOTES 1 TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled 2 TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic sto...

Page 69: ...s Hold Time from either RD WR or DS Inactive to CS Inactive t4 0 ns Hold Time from CS Inactive to Data Bus 3 state t5 5 20 ns Wait Time from either WR or DS Active to Latch Data t6 75 ns Data Set Up T...

Page 70: ...VALID t9 10 ns min MOTOROLA BUS READ AC TIMING BTS 1 MUX 0 Figure 14 12 A0 TO A7 D0 TO D7 R W CS DS ADDRESS VALID DATA VALID 0 ns min 0 ns min 0 ns min 75 ns max 5 ns min 20 ns max t1 t2 t3 t4 t5 MOT...

Page 71: ...DS2154 071498 71 71 DS2154 100 PIN LQFP PKG 100 PIN DIM MIN MAX A 1 60 A1 0 05 A2 1 35 1 45 B 0 17 0 27 C 0 09 0 20 D 15 80 16 20 D1 14 00 BSC E 15 80 16 20 E1 14 00 BSC e 0 50 BSC L 0 45 0 75 B...

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