DS2154
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TCBRs=0). See the Transmit Data Flow diagram in
Section 13 for more details.
7.2
HARDWARE BASED SIGNALING
7.2.1
Receive Side
In the receive side of the hardware based signaling,
there are two operating modes for the signaling buffer;
signaling extraction and signaling re–insertion. Signal-
ing extraction involves pulling the the signaling bits from
the receive data stream and buffering them over a 2 mul-
tiframe buffer and outputing them in a serial PCM fash-
ion on a channel–by–channel basis at the RSIG output
pin. This mode is always enabled. In this mode, the
receive elastic store may be enabled or disabled. If the
receive elastic store is enabled, then the backplane
clock (RSYSCLK) must be 2.048 MHz. The ABCD
signaling bits are output on RSIG in the lower nibble of
each channel. See the timing diagrams in Section 13 for
an example. The RSIG data is updated once a multi-
frame (2 ms) unless a freeze is in effect.
The other hardware based signaling operating mode
called signaling re–insertion can be invoked by setting
the RSRE control bit high (CCR3.3=1). In this mode, the
user will provide a multiframe sync at the RSYNC pin
and the signaling data will be re–aligned in the PCM
data stream provided at the RSER output pin according
to this applied multiframe boundary. In this mode, the
elastic store must be enabled and the backplane clock
(RSYSCLK) must be 2.048 MHz.
The signaling data in the two multiframe buffer will be
frozen in a known good state upon either a loss of syn-
chronization (OOF event), carrier loss, or frame slip. To
allow this freeze action to occur, the RFE control bit
(CCR2.0) should be set high. The user can force a
freeze by setting the RFF control bit (CCR2.1) high.
Setting the RFF bit high causes the same freezing
action as if a loss of synchronization, carrier loss, or slip
has occurred. The RSIGF output pin provides a hard-
ware indication that a freeze is in effect. The RSIGF pin
will go high immediately upon detection of any of the
events that can cause a freeze to occur. The RSIGF pin
will return low 3 ms to 5 ms after the event subsides. The
RSIGF pin action cannot be disabled.
The 2 multiframe buffer provides an approximate 1 mul-
tiframe delay in the signaling bits provided at the RSIG
pin (and at the RSER pin if RSRE=1 via CCR3.3). When
freezing is enabled (RFE=1), the signaling data will be
held in the last known good state until the corrupting
error condition subsides. When the error condition sub-
sides, the signaling data will be held in the old state for
an additional 3 ms to 5 ms before being allowed to be
updated with new signaling data.
7.2.2
Transmit Side
Via the THSE control bit (CCR3.2), the DS2154 can be
set up to take the signaling data presented at the TSIG
pin and insert the signaling data into the PCM data
stream that is being input at the TSER pin. The hard-
ware signaling insertion capabilities of the DS2154 are
available whether the transmit side elastic store is
enabled or disabled. If the transmit side elastic store is
enabled, the backplane clock (TSYSCLK) must be
2.048 MHz.
When hardware signaling insertion is enabled on the
DS2154 (TSRE=1), then the user must enable the
Transmit Channel Blocking Register Function Select
(TCBFS) control bit (CCR3.6=1). This is needed so that
the CAS multiframe alignment word, multiframe remote
alarm, and spare bits can be added to timeslot 16 in
frame 0 of the multiframe. The TS1 register should be
programmed with the proper information. If CCR3.6=1,
then a zero in the TCBRs implies that signaling data is to
be sourced from TSER (or TSIG if CCR3.2=1) and a one
implies that signaling data for that channel is to be
sourced from the Transmit Signaling (TS) registers.
See definition below.
