7.Electrical Interface
© China Daheng Group, Inc. Beijing Image Vision Technology Branch 17
The polarity of GPIO pins cannot be reversed, otherwise, camera or other peripherals could burn
out.
7.3.1.1.
Line0 (Opto-isolated Input) Circuit
Hardware schematics of opto-isolated input circuit is shown as Figure 7-1.
1
4
3
2
3.3V
Line0+
Line0-
FPGA INPUT0
Camera internal circuit
5V-24V
External circuit
Figure 7-1 Opto-isolated input circuit
⚫
Logic 0 input voltage: 0V~+2.5V (Line0+ voltage)
⚫
Logic 1 input voltage: +5V~+24V (Line0+ voltage)
⚫
Minimum input current: 7mA
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The status is unstable when input voltage is between 2.5V and 5V, which should be avoided
⚫
When peak voltage of input signal over 9V, a current limiting resistor is recommended to protect the
input Line0+. The recommended resistance is shown in Table 7-3
External input voltage
Circuit-limiting resistance Rlimit
Line0+ input voltage
9V
680Ω
About 5.5V
12V
1kΩ
About 6V
24V
2kΩ
About 10V
Table 7-3 Circuit-limiting resistor value
The connection method of the opto-isolated input circuit and the NPN and PNP photosensor is shown in
Figure 7-2 and Figure 7-3. The relationship between the pull-up resistor and the external power supply
voltage is shown in Table 7-3.
