7.Electrical Interface
© China Daheng Group, Inc. Beijing Image Vision Technology Branch 18
1
4
3
2
External circuit
Signal output
Power+
GND
NPN
Pull-up
resistor
3.3V
Line0+
Line0-
FPGA INPUT0
Camera internal circuit
Figure 7-2 NPN photosensor connected to opto-isolated input circuit
1
4
3
2
External circuit
Signal output
Power+
GND
PNP
3.3V
Line0+
Line0-
FPGA INPUT0
Camera internal circuit
Figure 7-3 PNP photosensor connected to opto-isolated input circuit
⚫
Rising edge delay: <50μs (0°C~45°C), parameter description as shown in Figure 7-4
⚫
Falling edge delay: <50μs (0°C~45°C), parameter description as shown in Figure 7-4
⚫
Different environment temperature and input voltage have influence on delay time of opto-isolated input
circuit. Delay times in typical application environment (temperature is 25°C) is as shown in
Parameter
Test condition
Value (us)
Rising edge delay
VIN=5V
3.02
~
6.96
VIN=12V
2.46
~
5.14
Falling edge delay
VIN=5V
6.12
~
17.71
VIN=12V
8.93
~
19.73
Table 7-4 Delay time of opto-isolated input circuit in typical application environment
