7. Internal Block Diagram of ICs
Model : DV-115
LA7952
NJM2068
NJU7313A
PRELIMINARY
MITSUBISHI
SYSTEM BLOCK DIAGRAM
-com
interface
SRout
CLK
DATA
SLout
R in
C in
tone
volume
LATCH
L in
SL in
SR in
SW in
SWout
Cout
Rout
Lout
BYPASS1
BYPASS2
volume
M62446FP
PRELIMINARY
DGND
CLK
DATA
LATCH
DVDD
OUT4
OUT1
OUT2
OUT3
AVDD
LBASS1
LBASS2
LBASS3
LTRE
BYPASSL
BYPASSR
Lin
Rin
GNDL
GNDR
Cin
GNDC
SLin
SRin
GNDS
SWin
AVSS
AGND
Lout
Rout
Cout
SLout
SRout
RBASS1
RBASS2
RBASS3
RTRE
CL2
CL1
CR2
CR1
SW out
21
20
19
18
17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
tone
tone
volume
volume
volume
volume
volume
volume
MCU
I/F
OUT-
PUT
PORT
16
7. Internal Block Diagram of ICs
Model : DV-115
HY57V161610DTC-8
Column Addr.
Latch & Counter
Burst Length
Counter
Refresh
Interval Timer
Refresh
Counter
D Q 0
D Q 1
D Q 2
D Q 3
D Q 4
D Q 5
D Q 6
D Q 7
D Q 8
D Q 9
D Q 1 0
D Q 1 1
D Q 1 2
D Q 1 3
D Q 1 4
D Q 1 5
Address
Register
I/O Control
Test Mode
Mode Register
Self Refresh Counter
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 0
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 1
RAS
CAS
CS
W E
U D Q M
L D Q M
CKE
Precharge
Overflow
Column Active
Row Active
Address[0:10]
CLK
BA(A11)
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
50pin TSOP-II
400mil x 825mil
0.8mm pin pitch
A2
A3
VDD
A5
A4
VSS
23
24
25
28
27
26
11
11
