7. Internal Block Diagram of ICs
Model : DV-115
RAM
1536 BYTES
SPC 700
CPU CORE
IN
T
E
RRUP
T C
O
NT
RO
L
L
E
R
A/D CONVERTER
SERIAL
INTERFACE
UNIT 0
SERIAL INTERFACE UNIT 1
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
14 BIT PWM GENERATOR
16 BIT CAPTURE
TIMER/COUNTER 2
IN
T
3
/N
M
I
IN
T
1
IN
T
0
IN
T
2
AN0 to AN7
8
PA0 to PA7
FIFO
FIFO
REMOCON
FDP
CONTROLLER/
DRIVER
32KHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RS
T
V
D
D
V
S
S
PO
R
T
A
PO
R
T
B
PO
R
T
C
PO
R
T
D
PO
R
T
E
PO
R
T
F
PO
R
T
G
PO
RT
H
8
8
6
2
8
8
8
8
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE5
PF0 to PF7
PG0 to PG7
PH0 to PH7
PE6 to PE7
TE
X
EXT
AL
XT
AL
TX
AV
R
EF
AV
S
S
G0/A0 to G15/A15
A16 to A23
A24 to A55
V
FDP
KR0 to KR7
PWM
RMC
CS0
SI0
SO0
SCK0
SI1
SO1
SCK1
EC0
TO
CINT
EC1
ADJ
2
2
16
8
ROM
32K/40K
/52K/60K
BYTES
32
8
RAM
RAM
KEY SCAN
8
2
CLOCK GENERATOR
/SYSTEM CONTROL
2
CXP8286
G1/A1
G0/A0
NC
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
PE6/PWM
PE7/TO/ADJ
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
AV
REF
PA0/AN0
PA1/AN1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31 32 33
41 42 43 44 45 46 47 48 49 50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
81
82
83
84
75
76
77
78
88 87 86 85
79
80
89
90
100 99 98 97 96 95 94
91
92
93
1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AV
S
S
RST
EXTAL
XTAL
Vss
TX
TEX
V
D
D
V
F
D
P
PD0/A55
PD1/A54
PD2/A53
PD3/A52
PD4/A51
A21
A22
A23
PH7/A24
PH6/A25
PH5/A26
PH4/A27
PH3/A28
PH2/A29
PH1/A30
PH0/A31
PG7/A32
PG6/A33
PG5/A34
PG4/A35
PG3/A36
PG2/A37
PG1/A38
PG0/A39
PF7/A40
PF6/A41
PF5/A42
PF4/A43
PF3/A44
PF2/A45
PF1/A46
PF0/A47
PD7/A48
PD6/A49
PD5/A50
G2/A2
G3/A3
G4/A4
G5/A5
G6/A6
G7/A7
G8/A8
G9/A9
G10/A10
G11/A11
G12/A12
V
D
D
G13/A13
G14/A14
G15/A15
A16
A17
A18
A19
A20
7. Internal Block Diagram of ICs
Model : DV-115
Volume Control
Interpolation Filter
DAC
Analog Filter
Control Port
Volume Control
Interpolation Filter
Analog Filter
Se
ri
al
P
o
rt
SCL/CCLK
MUTEC
AD0/CS
AOUTA
AOUTB
RST
LRCK
SDATA
MCLK
SDA/CDIN
DAC
External
Mute Control
SCLK
Mixer
2
CS434
C
O
15
2
14
3
13
4
16
1
11
6
10
7
9
8
12
5
Reset
RST
MUTEC
Mute Control
Serial Data
SDATA
AOUTA
Analog Output A
Serial Clock
SCLK
VA
Analog Power
ft/Right Clock
LRCK
AGND
Analog Ground
Master Clock
MCLK
AOUTB
Analog Output B
SCL/CCLK
SCL/CCLK
REF_GND Reference Ground
SDA/CDIN
SDA/CDIN
VQ
Quiescent Voltage
AD0/CS
AD0/CS
FILT+
Positive Voltage Reference
CS4955
CLK
ISET
DGND
SCL
SDA
PDAT[7:0]
RD
WR
ADDR
XTAL_OUT
VD[7:0]
HSYNC
VSYNC
FIELD
INT
RESET
I
2
C Interface
Host
Parallel
Interface
Color Sub-carrier Synthesizer
8
Video Formatter
Control
Registers
Chroma Modulate
Chroma Amplifier
Output
Interpolate
LPF
Burst Insert
Chroma Interpolate
LPF
Luma Interpolate
Luma Amplifier
Sync Insert
U,V
Y
Video Timing
Generator
TEST
Current
Reference
Voltage
Reference
VREF
R
DAC
Y
DAC
CVBS
DAC
C
10-Bit
DAC
VAA
XTAL_IN
Teletext
Encoder
TTXRQ
TTXDAT
YCbCr to RBG
B
DAC
G
DAC
10-Bit
10-Bit
10-Bit
10-Bit
10-Bit
RGB
RGB
Y
Y
8
Color Space
Converter
B
CVBS
GNDA
VAA
C
Y
V0
V1
V2
V3
V4
V5
V6
V7
FIELD /CB
HSYNC/CB
VSYNC
INT
TEST
XTAL_OUT
XTAL_IN
PADR
VDD
GNDD
GNDA
VAA
G
R
VREF
ISET
VAA
GNDA
RESET
SCL
SDA
TTXRQ
TTXDAT
CLKIN
WR
RD
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
PDAT6
PDAT7
CS4954-CQ
CS4955-CQ
48-Pin TQFP
Top View
48 47 46 45 44 43
41
42
40 39 38 37
13 14 15 16 17 18
20
19
21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
ES56033
11
11
