9
ARM 7500
T h e A R M 7 5 0 0 is use d for the b a sic p ro ce sso r in D a e w o o IN T E R N E T S e tto p b o x D S N -3 0 0A .
T h e A R M 7 5 0 0 is a m u ltim e dia pro ce sso r im p le m en te d o n a ch ip . A ch ip is com p o se d of im a g e a n d so u nd
tre a tm e n t p a rt, an d o th e r I/O tre atm e n t p arts, ce n terin g th e A R M 71 0 C C P U co re. T h e im a g e tre a tm e n t p a rt
ca n d isp la y the scree n s o f m o n ito rs, T V s o r L C D s.
T h e I/O tre a tm e n t pa rt is u se d for in terface s o f ke yb oa rds o r joy sticks.
T h e b lo ck d ia g ra m of th e A R M 7 5 0 0 is a s fo llo w :
T h e A R M 7 10 C is a 3 2-b it R IS C m ic ro p ro ce sso r m o d u le . T h is h a s a 4 K byte ca ch e, w rite b u ffer a n d A R M 7
p ro ce sso r co re w ith M e m o ry M a n a g em e nt U n it (M M U ). T h e im a ge b lo ck c an d rive h ig h-le ve l C D T s o r lo w -
vo lta g e L C D disp la yin g d e vice s. T h e im a g e m od u le ca n o b tain m an y kin d s o f fre q u e nc ie s b e ca u se it is d e -
sign e d to d rive a V o lta g e C o n tro lle d O scilla to r (V C O ) in ord er to su p p ly th e m a ste r freq u e n cy. T h e so u nd
b lo ck h a s a n 8 -b it a n a lo gu e ste re o s yste m a n d a 3 2 -b it se ria l so u n d inte rfa ce su ita ble to d rive th e e xte rn a l
C D D A C . T h e clo ck co n tro l is fle xib ly d e sig n ed a nd is divid ed in to a C P U co re cloc k in p u t a n d th e in p u t/o u tpu t
sy stem clo ck inc lu ding th e m e m ory sys te m clo ck a n d im ag e in p ut. T he p o w e r c on tro l h a s tw o m o de s. T he
cloc k in p u tting in to the C P U is su sp en d e d b u t d isp la y fu n ctio n is o n in th e S U S P E N D m od e , A ll clo ck s a re
su sp e n de d in the S T O P m od e .
Interrupts & Timers
Clock & Power
Ti
m
ing
& C
loc
k
Serial portl
Serial portl
DMA
DRAM
Decode
ROM
4xA/D
I/O Ctl
Arbitration
Data Buffer
MMU
4KB Cache
ARM7
Write Buffer
Data Latch
Sound
FIFO
Video
FIFO
Cursor
FIFO
Sound
DACs
Video
Palette
Cursor
Palette
Sterep
Digital
RGB
DACs
LCD
MUX
IO & Memory
ARM704
CPUCLK
VidCLK
SndCLK
MemCLK
Reset
D[31:0]
DAC Ref
L/R DACs
Mute
Timing
RGB DACs
LCD
Serial
Wakeup
OSC Ctl
DRAM
ROMCS
Analogue
IOP[7:0]
A[28:0]
I/O Chip Select
PCMCIA XIF
IOD[15:0]
Interrupts
Summary of Contents for DSN-300A
Page 5: ...4 3 BLOCK DIAGRAM...
Page 37: ...36 10 EXPLODED VIEW 10 1 DSN 300A...
Page 39: ...38 10 2 MODEL DSN 300S...
Page 42: ...41 11 SCHEMATIC DIAGRAM...
Page 43: ...42...
Page 44: ...43...
Page 45: ...44...
Page 46: ...45...
Page 48: ......