Daewoo DSL19M1WC, Service Manual

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Pin Name No I/O Description
GPIO14/PWM3/
SCART16 52 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
Or it can be programmed to sense the Fast Blank Input signal from a SCART I/P source. When
not used, this pin is available as General Purpose Input/output Port.
TDO 55 O This Pin provides the Output Data in case of Boundary Scan Mode.
HSYNC1 156 I Horizontal Sync signal Input-1. Used when Analog RGB component signal carries separate
HSYNC signal.
VSYNC1 157 I Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate VSYNC
signal.
101 O Clock Output meant for External OSD Controller
102 O Horizontal Sync Output meant for External OSD Controller
XOSD_CLK 103 O Vertical Sync Output meant for External OSD Controller
XOSD_HS 104 O Field Signal Output meant for External OSD Controller
PD20/B4/GPIO0
PD21/B5/GPIO1
PD22/B6/GPIO2
PD23/B7/GPIO3 86
87
88
89 IO These Pins provide the Panel Data as shown in the TTL Display Interface Table below. These are
available as General Purpose Input / Output Pins when not used as Panel Data.
Table 6: LVDS Display Interface
Pin Name No I/O Description
PBIAS 53 O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
PPWR 54 O Panel Power Control [Tri-state output, 5V- tolerant]
AVDD_LV_33 56 DP Digital Power for LVDS Block. Connect to digital 3.3V supply.
VCO_LV 57 O Reserved. Output for Testing Purpose only at Factory.
AVSS_LV 58 G Ground for LVDS outputs.
AVDD_OUT_LV_33 59 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV_E 60 O
CH3N_LV_E 61 O
These form the Differential Data Output for Channel – 3 (Even).
CLKP_LV_E
62 O
CLKN_LV_E 63 O
These form the Differential Clock Output Even Channel.
CH2P_LV_E 64 O
CH2N_LV_E
65 O
These form the Differential Data Output for Channel – 2 (Even).
CH1P_LV_E 66 O
CH1N_LV_E 67 O
These form the Differential Data Output for Channel – 1 (Even).
CH0P_LV_E 68 O
CH0N_LV_E 69 O
These form the Differential Data Output for Channel – 0 (Even).
AVSS_OUT_LV
70 G Ground for LVDS outputs.
AVDD_OUT_LV_33 71 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
CH3P_LV_O 72 O
CH3N_LV_O
73 O
These form the Differential Data Output for Channel – 3 (Odd).
CLKP_LV_O 74 O
CLKN_LV_O 75 O
These form the Differential Clock Output Odd Channel.
CH2P_LV_O 76 O
CH2N_LV_O 77 O
These form the Differential Data Output for Channel – 2 (Odd).
CH1P_LV_O 78 O
CH1N_LV_O 79 O
These form the Differential Data Output for Channel – 1 (Odd).
CH0P_LV_O 80 O
CH0N_LV_O
81 O
These form the Differential Data Output for Channel – 0 (Odd).
AVSS_OUT_LV 82 G Ground for LVDS outputs.
AVDD_OUT_LV_33 83 DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.