Document Number: 002-00833 Rev. *L
Page 30 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
7.6
Writing Commands/Command Sequences
The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the system must drive CE#
and WE# to V
IL
and OE# to V
IH
when providing an address and data. While an address is valid, AVD# must be driven to V
IL
.
Addresses are latched on the rising edge of AVD#, data is latched on the rising edge of WE#.
All writes to the memory are single word length and follow asynchronous timing. However, it is allowed to leave the host and memory
interfaces in synchronous mode as long as the host synchronous timing for a single word synchronous write can meet the timing
requirements of the memory device write cycle. Generally a synchronous write would include Clock toggling during the write but, it is
also allowed for Clock to be at V
IL
during the write.
If the device is in the Synchronous Read Mode (CR.15 = 0), the addresses are latched on the rising edge of CLK when AVD# is at
V
IL
, while data is latched on the rising edge of WE#. If CLK is held at V
IL
, addresses are latched on the rising edge of AVD#. CLK
should not be held at V
IH
when writing commands while the device is in Synchronous Read Mode. See the
for the signal combinations that define each phase of a write bus operation to the device. Each write is a
command or part of a command sequence to the device. The address provided in each write operation may be a bit pattern used to
help identify the write as a command to the device. The upper portion of the address may also select the bank or sector in which the
command operation is to be performed. A
Bank Address
(BA) is the set of address bits required to uniquely select a bank. Similarly,
a
Sector Address
(SA) is the address bits required to uniquely select a sector. The data in each write identifies the command
operation to be performed or supplies information needed to perform the operation. See
Table 43, Command Definitions on page 57
for a listing of the commands accepted by the device. I
CC2
in
represents the active current
specification for an Embedded Algorithm operation.
7.7
Program/Erase Operations
When the Embedded Program algorithm is complete, the device returns to the calling routing (Erase Suspend, SSR Lock, Secure
Silicon Region, or Idle State).
The system can determine the status of the program operation by reading the Status Register. Refer to
for information on these status bits.
A
0
cannot be programmed back to a
1
. A succeeding read shows that the data is still
0.
Only erase operations can convert a
0
to
a
1
.
Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend, and
Status Read command. Any commands written to the device during the Embedded Erase Algorithm are ignored except Erase
Suspend and Status Read command. Reading from a bank that is not programming or erasing is allowed.
A hardware reset immediately terminates the program/erase operation and the program command sequence should be reinitiated
once the device has returned to the idle state, to ensure data integrity.
old data
0011
new
data
0101
results
0001
