Cypress S29VS128R Manual Download

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Document Number: 002-00833 Rev. *L

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S29VS256R
S29VS128R
S29XS256R
S29XS128R

7.2.5.2

Wait States

Configuration Register bits 14 to 11 (CR.[14..11]) define the number of delay cycles after the AVD# Low cycle that captures the initial
address until the cycle that read data is valid. The bits from 14 to 11 are in most to least significant order. The random address
access at the beginning of each read burst takes longer than the subsequent read cycles. The memory bus interface must be told
how many cycles to wait before driving valid data then advancing to the next data word. The number of initial wait cycles will vary
with the memory clock rate. The number of wait states is found in the wait state table information above. The minimum number of
wait cycles is three. The maximum is 13. The default after power-on or hardware reset is 13 cycles.

When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK. Subsequent words are
output t

BACC

after the rising edge of each successive clock cycle, which automatically increments the internal address counter.

7.2.5.3

RDY Polarity

Configuration Register bit 10 (CR.10) controls whether the RDY signal indicates valid data when High or when Low. When this bit is
zero the RDY signal indicates data is valid when the signal is Low. When this bit is one the RDY signal indicates data is valid when
the signal is High. The default for this bit is set to one after power-on or a hardware reset.

7.2.5.4

RDY Timing

Configuration Register bit 8 (CR.8) controls whether the RDY signal indicates valid data on the same cycle that data is valid or one
cycle before data is valid. When this bit is zero the RDY signal indicates data is valid in the same cycle the data is valid. When this
bit is one the RDY signal indicates data is valid one cycle before data is valid. The default for this bit is set to one after power-on or a
hardware reset.

7.2.5.5

Output Drive Strength

Configuration Register bit 7 (CR.7) controls whether the data outputs drive with full or half strength. When this bit is zero the data
outputs drive with full strength. When this bit is one the data outputs drive with half strength. The default for this bit is cleared to zero
after power-on or a hardware reset.

7.2.5.6

Burst Length

Configuration Register bits 2 to 0 (CR.[2..0]) define the length of burst read accesses. The bits from 2 to 0 are in most to least
significant order. See the register table for code meaning & default value.

7.3

Status Register

The status of program and erase operations is provided by a status register. A status register read command is written followed by a
read of the status register for each access of the status register information. The Clear Status Register Command will reset the
status register. The status register can be read in synchronous or asynchronous mode.

Notes:

1. Status bits higher than Bit 7 are undefined.
2. Bit 7 reflects the device status.
3. If the device is busy, Bit 0 is used to check whether the addressed bank is busy or some other bank is busy.
4. All the other bits reflect the status of the device.

Table 21. Status Register Reset State

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Device Ready

Bit.

Overall status