Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 97 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 97
TrueTouch Module
11.2.11 IDAC_D Register
The Current DAC Data Register (IDAC_D) specifies the 8-
bit multiplying factor that determines the output DAC cur-
rent.
Bits 7 to 0: IDACDATA[7:0].
The 8-bit value in this register
sets the current driven onto the analog global mux bus when
the current DAC mode is enabled.
For additional information, refer to the IDAC_D register on
page 256 .
11.3 Timing Diagrams
Figure 11-15. Event Timing (Mode = 00)
Figure 11-16. Pulse Width Frequency Timing (Mode = 01/10)
Figure 11-17. Continuous Timing (Mode = 11)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,FDh IDAC_D IDACDATA[7:0] RW : 00
SYSCLK
Block Enable
Count Enable
Event
Count 00 01 02 03 88 87 89 04
SYSCLK
Block Enable
Edge Detect
Count Enable
Count 00 01 02 95 94 96 03
Input Signal
SYSCLK
Block Enable
Count Enable
Count 00 01 02 45 44 00 03
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