Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 133 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 133
I2C Slave
15.4.6 Compatibility Mode Configuration
In compatibility mode, the SCL, as usual, is pulled low until the CPU responds by setting the Transmit/Receive bit and for
loading a byte in the I2C_DATA register (in case of transmit operation) even though IMO is operational.
Figure 15-13 illus-
trates the process of switching from direct clocking to sampled mode.
Figure 15-13. Direct Clocking to Sample Mode Timing
See the following notes regarding Figure 15-13 :.
a. After, the address matches IRQ and a signal called switch_to_sample_mode are asserted asynchronously.
b. This IRQ goes as input to the sleep controller block. The sleep controller block wakes the system by clearing the sleep
bit.
c. After IMO is operational, the signal switch_to_sample_mode is registered and asserted high, indicating IMO is opera-
tional. When this registered signal becomes high, the switch_to_sample_mode signal deasserts asynchronously.
d. The state machines and other logic are put at appropriate states when switching to sample mode.
IMO
rel_switch_sample_mode
switch_to_sample_mode
IRQ
SCL
SDA
SCL is released here if buffer mode is enabled, otherwise it is
released once CPU is operational and responds by setting the
transmit/receive bit. It thenloads the I2C_DATA register with a
byte if it is a transmit operation
0
[+] Feedback