Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 275
25. Digital Clocks
This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options
available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapter in the sec-
tion called
“PSoC Core” on page 31 . For a complete table of the digital clock registers, refer to the “Summary Table of the
System Resource Registers” on page 272 . For a quick reference of all PSoC registers in address order, refer to the Register
Details chapter on page 47 .
25.1 Architectural Description
The PSoC M8C core has a large number of clock sources
that increase the flexibility of the PSoC device, as listed in
Table 25-1 and illustrated in Figure 25-1 .
25.1.1 Internal Main Oscillator
The Internal Main Oscillator (IMO) is the foundation upon
which almost all other clock sources in the PSoC device are
based. The default mode of the IMO creates a 24 MHz refer-
ence clock that is used by many other circuits in the PSoC
device. The IMO may also be configured to operate in a PLL
mode where the oscillator is locked to a precision 32.768
kHz crystal reference. The PSoC device has an option to
replace the IMO with an externally supplied clock that
becomes the base for all of the clocks the IMO normally
serves. The internal base clock net is called SYSCLK and
may be driven by either the IMO or an external clock (EXT-
CLK).
Whether the external clock or the internal main oscillator is
selected, all PSoC device functions are clocked from a
derivative of SYSCLK or are resynchronized to SYSCLK. All
external asynchronous signals (through row inputs), as well
as the selected 32.768 kHz crystal oscillator, are resynchro-
nized to SYSCLK for use in the digital PSoC blocks.
Some PSoC devices contain the option to lower the internal
oscillator’s system clock from 24 MHz to 6 MHz. See the
“Architectural Description” on page 15 , in the Internal Main
Oscillator chapter, for more information.
The IMO is discussed in detail in the chapter “Internal Main
Oscillator (IMO)” on page 15 .
25.1.2 Internal Low Speed Oscillator
The Internal Low Speed Oscillator (ILO) is always on unless
the device is operating off an external crystal. The ILO is
available as a general clock, but is also the clock source for
the sleep and watchdog timers.
The ILO is discussed in detail in the chapter “Internal Low
Speed Oscillator (ILO)” on page 19 .
Table 25-1. System Clocking Signals and Definitions
Signal Definition
SYSCLKX2 Twice the frequency of SYSCLK.
SYSCLK Either the direct output of the Internal Main Oscillator or the
direct input of the EXTCLK pin while in external clocking
mode.
CPUCLK SYSCLK is divided down to one of eight possible frequencies
to create CPUCLK which determines the speed of the M8C.
See OSC_CR0 in the Register Definitions section of this
chapter.
VC1 SYSCLK is divided down to create Variable Clock 1 (VC1).
See OSC_CR1 in the Register Definitions section of this
chapter. Division range is from 1 to 16.
VC2 VC1 is divided down to create Variable Clock 2 (VC2). See
OSC_CR1 in the Register Definitions section of this chapter.
Division range is from 1 to 16.
VC3 Divides down either SYSCLK, VC1, VC2, or SYSCLKX2 to
create Variable Clock 3 (VC3). Division range is from 1 to
256. See OSC_CR3 and OSC_CR4 in the Register Defini-
tions section of this chapter.
CLK32K Either the Internal Low Speed Oscillators or the External
Crystal Oscillators output. See OSC_CR0 in the Register
Definitions section of this chapter.
CLK24M The internally generated 24 MHz clock by the IMO. By
default, this clock drives SYSCLK; however, an external clock
may be used by enabling EXTCLK mode. Also, the IMO may
be put into a slow mode using the SLIMO bit which changes
the speed of the IMO and the CLK24M to either 6 MHz or 12
MHz in some PSoC devices.
SLEEP One of four sleep intervals may be selected from 1.95 ms to 1
second. See OSC_CR0 in the Register Definitions section of
this chapter.