CYTVII-B-E-1M-176-CPU Evaluation Board User Guide, Document Number. 002-22883 Rev. *C
53
Schematics of Base Board
Figure C-15. Pin Header Section-01
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
PIN HEADER SECTION -01
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
VCC_5V
VCC_5V
VCC_5V
VCC_5V
VCC_5V
VCC_5V
BB_USER_BUTTON_4
4,16
LIN4_RXD
5,12
LIN3_WAKE
5,11
LIN3_RXD
5,11
LIN2_WAKE
5,11
LIN2_RXD
5,11
LIN4_TXD
5,12
LIN3_SLP
5,11
LIN3_TXD
5,11
LIN2_SLP
5,11
LIN2_TXD
5,11
BB_I2C1_SCL
5
BB_I2C1_SDA
5
LIN4_SLP
5,12
LIN4_WAKE
5,12
SPI0_WP
5,15
SUPPLY_INH
5,14
LIN0_RXD
5,10
LIN0_TXD
5,10
LIN0_WAKE
5,10
LIN0_SLP
5,10
CXPI_RXD
5,15
CXPI_TXD 5,15
LIN5_RXD
5,12
LIN5_TXD 5,12
LIN5_WAKE
5,12
LIN5_SLP
5,12
CXPI_SELMS
5,15
CXPI_NSLP
5,15
BB_HPMC_2
5
BB_HPMC_3
5
BB_HPMC_1
5
BB_HPMC_4
5
BB_PWM_2
4
BB_PWM_4
4
BB_PWM_6
4
BB_PWM_1
4
BB_PWM_3
4
BB_PWM_5
4
BB_PWM_7
4
BB_ADC_2
4
BB_ADC_4
4
BB_ADC_6
4
BB_ADC_8
4
BB_ADC_3
4
BB_ADC_5
4
BB_ADC_7
4
UART1_TX
4
UART1_RX 4
UART1_CTS
4
UART1_RTS 4
CAN2_RXD
4,6
CAN2_TXD 4,6
CAN_SPI1_SS1
4,8
CAN_SPI1_SS0
4,8
CAN2_S
4,6
CAN_SPI1_SS2
4,9
CAN4_S
4,7
CAN3_S
4,6
CAN8_WAKE
4,9
CAN5_S
4,7
CAN9_WAKE
4,9
CAN5_RXD
4,7
CAN4_RXD
4,7
DEBUG_GPIO_3
4
DEBUG_GPIO_1
4
BB_USER_BUTTON_2
5,16
BB_USER_BUTTON_5
5,16
CAN5_TXD 4,7
CAN4_TXD 4,7
DEBUG_GPIO_4
4
DEBUG_GPIO_2
4
BB_USER_BUTTON_1
5,16
BB_USER_BUTTON_3
5,16
CAN6_WAKE
4,8
CAN7_WAKE
4,8
SPI0_CLK
4,15
SPI0_SS
4,15
LIN1_SLP
5,10
LIN1_WAKE
5,10
CAN0_S
5,6
BB_USER_LED9
5,16
BB_USER_LED8
5,16
CAN1_RXD
5,6
CAN1_TXD
5,6
CAN1_S
5,6
CAN0_RXD
5,6
CAN0_TXD 5,6
BB_ADC_9
5
LIN1_TXD 5,10
LIN1_RXD
5,10
BB_ADC_10
5
BB_ADC_11
5
SCH Title :
Size
Document Number
R e v
Date:
Sheet
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CYPRESS SEMICONDUCTOR © 2019
Page Title :
Drawn By
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
Approved By
A
TRAVEO II BASE BOARD
B
17
18
Wednesday, November 20, 2019
PIN HEADER SECTION-01
BALA K
SHANTANU
SCH Title :
Size
Document Number
R e v
Date:
Sheet
o f
CYPRESS SEMICONDUCTOR © 2019
Page Title :
Drawn By
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
Approved By
A
TRAVEO II BASE BOARD
B
17
18
Wednesday, November 20, 2019
PIN HEADER SECTION-01
BALA K
SHANTANU
SCH Title :
Size
Document Number
R e v
Date:
Sheet
o f
CYPRESS SEMICONDUCTOR © 2019
Page Title :
Drawn By
CYPRESS SEMICONDUCTOR
198 CHAMPION COURT
SAN JOSE, CA 95134
(408) 943-2600
Approved By
A
TRAVEO II BASE BOARD
B
17
18
Wednesday, November 20, 2019
PIN HEADER SECTION-01
BALA K
SHANTANU
JP9
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
JP6
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
JP1
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
JP11
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
JP10
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
JP2
HDR_2X10
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19