Cypress CYTVII-B-E-100-SO, User Manual, Page: 13 / 60

CYTVII-B-E-100-SO Evaluation Board User Guide, Document Number: 002-28207 Rev. *A 13
Connections and Settings
The first column in Table 4-1 lists the pin number on the MCU, followed by the port pin name.
The Access Pin on Baseboard column indicates the place where the signal can be probed on the baseboard. For example, JP6.15 refers to the 15th pin on the JP6 header.
A value of N/A in the Access Pin on Baseboard column indicates that the signal is unavailable on the JPx pin header on the baseboard. The signal might still be available
on separate pin headers near the respective peripheral. For example, CAN7_RXD, CAN7_TXD.
For details on the alternate functionality of each MCU pin, see the device datasheet.
Note: If there are pins with more than one connection to the baseboard, make sure that no two peripherals are driven at the same time. The unused peripheral jumpers
must be disconnected before using the other connection.
P21.5 PWM_37/PWM_38_N/TC_37_TR0/TC_38_TR1 JP1.3
P22.0 PWM_34/PWM_35_N/TC_34_TR0/TC_35_TR1/SCB6_RX/SCB6_MISO/CAN1_1_TX JP4.6
P22.1 PWM_33/PWM_34_N/TC_33_TR0/TC_34_TR1/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN1_1_RX JP4.8
P22.2 PWM_32/PWM_33_N/TC_32_TR0/TC_33_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK JP4.10
P22.3 PWM_31/PWM_32_N/TC_31_TR0/TC_32_TR1/SCB6_CTS/SCB6_SEL0 JP4.12
P23.3 PWM_M_11/PWM_M_10_N/TC_M_11_TR0/TC_M_10_TR1/FAULT_OUT_3/TRIG_IN[30] JP7.10
P23.4 PWM_25/PWM_M_11_N/TC_25_TR0/TC_M_11_TR1/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31] JP4.7
P23.5 PWM_24/PWM_25_N/TC_24_TR0/TC_25_TR1/SWJ_SWCLK_TCLK N/A
P23.6 PWM_23/PWM_24_N/TC_23_TR0/TC_24_TR1/SWJ_SWDIO_TMS N/A
P23.7 PWM_22/PWM_23_N/TC_22_TR0/TC_23_TR1/CAL_SUP_NZ/SWJ_SWDOE_TDI/EXT_CLK/HIBERNATE_WAKEUP[1] JP4.9
VCCD VCCD N/A
VDDA VDDA N/A
VDDD VDDD N/A
VDDIO VDDIO N/A
VREFH VREFH N/A
VREFL VREFL N/A
VSSA VSSA/VSSD/VSSIO/Ground JP1.19
XRES XRES JP12.16
Table 4-1. Device Port Pin Connections on Baseboard
Port Pin Pin Function
Access Pin
on
Baseboard