Cypress CY8CPROTO-062S3-4343W Manual Download

Page: 12 / 39

CY8CPROTO-062S3-4343W PSoC 62S3 Wi-Fi BT Prototyping Kit Guide, Doc. # 002-28070 Rev. *A

Introduction

Table 1-1. Pioneer Board Pinout

Pin

Primary On-board

Function

Secondary On-board

Function

Connection details

PSoC 6 MCU Pins

XRES

Hardware Reset

–

Remove R49 to disconnect it from
KitProg3 RESET.

P0[4]

User Button with

Hibernate wakeup

capability

–

Configured as Active LOW switch

P5[0]

GPIO

–

P5[1]

GPIO

–

P5[6]

GPIO

–

P5[7]

GPIO

–

P6[4]

I2C SCL

–

Remove R21 to disconnect from
KitProg3 I2C_SCL

P6[5]

I2C SDA

–

Remove R30 to disconnect from
KitProg3 I2C_SDA

P6[6]

SWDIO

GPIO

–

P6[7]

SWDCLK

GPIO

–

P8[0]

CapSense Button0

GPIO

Connected to CapSense by default.
Remove R84 to disconnect CapSense.

P8[1]

CapSense Button1

GPIO

Connected to CapSense by default.
Remove R77 to disconnect CapSense.

P7[0]

CapSense Silder0

GPIO

Connected to CapSense by default.
Remove R82 to disconnect CapSense.

P7[1]

CapSense Silder1

GPIO

Connected to CapSense by default.
Remove R81 to disconnect CapSense.

P7[2]

CapSense Silder2

GPIO

Connected to CapSense by default.
Remove R80 to disconnect CapSense.

P7[3]

CapSense Silder3

GPIO

Connected to CapSense by default.
Remove R79 to disconnect CapSense.

P9[0]

CapSense Silder4

GPIO

Connected to CapSense by default.
Remove R78 to disconnect CapSense.

P9[1]

GPIO

–

P7[7]

CMOD

–

P10[0]

UART RX

GPIO

Connected to KitProg3 UART TX pin.
Remove R53 to disconnect from
KitProg3.

P10[1]

UART TX

GPIO

Connected to KitProg3 UART RX pin.
Remove R64 to disconnect from
KitProg3.

P10[2]

GPIO

UART RTS

Populate R29 to connect to KitProg3
UART CTS.

Summary of Contents for CY8CPROTO-062S3-4343W

Page 1: ...ROTO 062S3 4343W PSoC 62S3 Wi Fi BT Prototyping Kit Guide Doc 002 28070 Rev A Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 800 858 1810 Phone Intnl 1 408 943 2600 www cypress com ...

Page 2: ...l and hereby do release Cypress from any claim damage or other liability arising from any Security Breach In addition the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications To the extent permitted by applicable law Cypress reserves the right to make changes to this document without further ...

Page 3: ...tProg3 On Board Programmer Debugger 20 2 2 1 Programming and Debugging using ModusToolbox IDE 20 2 2 2 USB UART Bridge 24 2 2 3 USB I2C Bridge 24 3 Hardware 25 3 1 Schematics 25 3 2 Hardware Functional Description 25 3 2 1 CY8CMOD 062S3 4343W MOD1 25 3 2 2 PSoC 5LP based KitProg3 U2 29 3 2 3 Serial Interconnection between PSoC 5LP and PSoC 6 MCU 30 3 2 4 Power Supply System 31 3 2 5 Expansion Conn...

Page 4: ...he factory has been verified to meet with the requirements of CE as a Class A product PSoC 62S3 Wi Fi BT Prototyping Boards contain electrostatic discharge ESD sensitive devices Electrostatic charges readily accumulate on the human body and any equipment which can cause a discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD precautions ar...

Page 5: ...ansmit and receive radio signals in accordance with the spectrum regulations for the 2 4 GHz unlicensed frequency range Cypress Semiconductor Corporation has obtained regulatory approvals for this kit to be used in specific countries These countries include the United States FCC Part 15 Canada IC RSS210 and Japan JRF TELEC Additional regional regulatory agency approval may be required to operate t...

Page 6: ... device may not cause interference This device must accept any interference including interference that may cause undesired oper ation of the device This equipment complies with radio frequency exposure limits set forth by Industry Canada for an uncontrolled environment This equipment should be installed and operated with minimum distance 20 cm between the device and the user or bystanders CAUTION...

Page 7: ...g Kit Guide Doc 002 28070 Rev A 7 Japan TELEC This product has built in specified radio equipment which authorized Japan Radio Certification certification number 001 P00840 based on type approval system Manufactured by Murata Manufacturing 001 P00840 R ...

Page 8: ...gher flexibility in field tuning of the design and faster time to market The PSoC 6 MCU on this kit has 512 KB of Flash and 256 KB of SRAM The PSoC 62S3 Wi Fi BT Kit carries a PSoC 6 MCU and a CYW4343W based Wi Fi and Bluetooth combination module In addition the board features an onboard programmer debugger KitProg3 a 512 MB Quad SPI NOR flash a Micro B connector for USB device interface a 5 segme...

Page 9: ...S3 Wi Fi BT Prototyping Kit package has the following contents as shown in Figure 1 1 PSoC 62S3 Wi Fi BT Prototyping Board USB Type A to Micro B cable Quick Start Guide Figure 1 1 Kit Contents Inspect the contents of the kit if you find any part missing contact your nearest Cypress sales office for help www cypress com support ...

Page 10: ...ent development ecosystems refer to the kit webpage ModusToolbox is a free development ecosystem that includes the ModusToolbox IDE and the PSoC 6 SDK Using ModusToolbox IDE you can enable and configure device resources middleware libraries and program and debug the device You can download the software from the ModusToolbox home page See the ModusToolbox Installation Guide for additional informati...

Page 11: ...orted One user LED one user button and a reset button for PSoC 6 MCU One Mode selection button and one Status LED for KitProg3 Refer to Figure 2 4 for more details of the kit features Figure 1 2 shows the pinout of the PSoC 62S3 Wi Fi BT Kit Figure 1 2 Prototyping Kit Pinout VCC_5V VCC_3V6 J9 J4 J6 J2 J1 GND VBACKUP GND NC NC BT_I2S_DI BT_I2S_DO BT_I2S_WS BT_I2S_CLK BT_GPIO_5 BT_GPIO_4 BT_GPIO_3 N...

Page 12: ...nnect CapSense P8 1 CapSense Button1 GPIO Connected to CapSense by default Remove R77 to disconnect CapSense P7 0 CapSense Silder0 GPIO Connected to CapSense by default Remove R82 to disconnect CapSense P7 1 CapSense Silder1 GPIO Connected to CapSense by default Remove R81 to disconnect CapSense P7 2 CapSense Silder2 GPIO Connected to CapSense by default Remove R80 to disconnect CapSense P7 3 CapS...

Page 13: ...S device interface USB_DM USB FS device interface CYW4343 Pins BT_UART_TXD UART interface with Host MCU PSoC 6 MCU Connected to UART RX pin P3 0 of PSoC 6 MCU by default To connect to KitProg3 remove R64 and populate R63 BT_UART_RXD UART interface with Host MCU PSoC 6 MCU Connected to UART TX pin P3 1 of PSoC 6 MCU by default To connect to KitProg3 remove R53 and populate R52 BT_UART_CTS UART inte...

Page 14: ...t routed on to the castellated pads on CY8CMOD 062S3 4343W carrier module Hence this pin is NC on the kit BT_GPIO_3 Bluetooth GPIO BT_GPIO_4 Bluetooth GPIO BT_GPIO_5 Bluetooth GPIO WL_IO_1 GPIO Table 1 2 Document Conventions for Guides Convention Usage Courier New Displays file locations user entered text and source code C cd icc Italics Displays file names and reference documentation Read about t...

Page 15: ...uman Interface Device I2C Inter Integrated Circuit I2S Inter IC Sound IC Integrated Circuit IDE Integrated Development Environment IoT Internet of Things LED Light emitting Diode LPO Low Power Oscillator OOB Out Of Box PC Personal Computer PSoC Programmable System on Chip PWM Pulse Width Modulation QSPI Quad Serial Peripheral Interface SAR Successive Approximation Register SDHC Secure Digital Host...

Page 16: ...onnect Multi Layer AHB IPC MPU SMPU CRYPTO AES SHA CRC TRNG RSA ECC Initiator MMIO High Speed I O Matrix Smart I O Boundary Scan 1x SCB I2C SPI PSoC 62 CY8C62x5 Digital DFT Test Analog DFT System Resources Power Reset Sleep Control PWRSYS LP ULP REF POR Reset Control TestMode Entry XRES LVD BOD DeepSleep Hibernate Active Sleep LowePowerActive Sleep Power Modes Backup OVP Clock Clock Control IMO WD...

Page 17: ...mit Switch 2x CapSense button 5 Segment CapSense Slider I2C EEPROM QSPI Flash User LED Micro USB Voltage Selection Jumper Current Measurement 1 8V LDO 3 3V LDO 3 6V Buck 4 7K Pull up 4 7K Pull up Power LED Mode Switch Status LED IO Header UART H W Flow Control Level Translator Power LED Micro USB Current limit Switch 5 pin Header 5 pin Header USB 10 pin JTAG SWD Cypress PSoC 6 MCU Oscillator 32KHz...

Page 18: ...C bridge and USB UART bridge For more details see the KitProg3 User Guide 5 KitProg3 5 pin programming header J5 This header brings out the SWD interface pins of the KitProg3 This is used to program and debug the PSoC 6 MCU If KitProg3 section is broken away it can be used to program any device over the 5 pin interface Please note that VTARG is an input to KitProg3 and hence target must be powered...

Page 19: ...nput from the external supply should be between 3 6 V and 5 V Note that this is not required when powering via one of the two Micro USB connectors on the board 15 Power LEDs LED1 LED3 LED1 and LED3 are amber LEDs that indicate the status of power supplied to PSoC 5LP and PSoC 6 MCU respectively 16 PSoC 6 USB device connector J10 The USB cable provided with the PSoC 62S3 Wi Fi BT Prototyping Kit ca...

Page 20: ...mple which is the Out Of Box OOB project of this kit to illustrate programming and debugging in ModusToolbox IDE 1 Connect the board to the PC using the USB cable as shown in Figure 2 5 It enumerates as a USB Composite Device if you are connecting it to your PC for the first time KitProg3 can operate either in CMSIS DAP Bulk mode default or CMSIS DAP HID mode or DAPLink mode Programming is faster ...

Page 21: ...igure 2 7 Figure 2 7 New Application Creation Choose Target Hardware c Select the desired application in the Starter Application window and click Next as shown in Figure 2 8 If desired you can change the application name in this window Figure 2 8 New Application Creation Select Starter Application d Click Finish in the Summary window as shown in Figure 2 9 Figure 2 9 New Application Creation Summa...

Page 22: ... configuration as shown in Figure 2 10 Figure 2 10 Programming in ModusToolbox 4 ModusToolbox has an integrated debugger To debug a PSoC 6 MCU application in the Project Explorer select App_Name project In the Quick Panel scroll to the Launches section and click the App_Name Debug KitProg3 configuration as shown in Figure 2 11 Note that Debug operation would perform a build operation followed by p...

Page 23: ... ModusToolbox IDE on page 20 for programming the board 1 Connect the board to your PC using the provided USB cable through the KitProg3 USB connector 2 Open a terminal program and select the KitProg3 COM port Set the serial port parameters to 8N1 and 115200 baud 3 Press the reset button SW1 on the board and confirm that Hello World and other text is displayed on the UART terminal as shown in Figur...

Page 24: ...ion between KitProg3 and PSoC 6 MCU 2 2 3 USB I2C Bridge The KitProg3 can function as a USB I2C bridge and communicate with the Bridge Control Panel BCP software The I2C lines on the PSoC 6 MCU are hard wired on the board to the I2C lines of the KitProg3 with onboard pull up resistors as Figure 2 14 shows The USB I2C supports I2C speeds of 50 kHz 100 kHz 400 kHz and 1 MHz For more details on the K...

Page 25: ...working of PSoC 6 MCU and CYW4343W A Pre certified Type 1DX module with CYW4343W from Murata LBEE5KL1DX is used for ease of development CYW4343W supports only 2 45GHz band but the antenna used is 2450AD14A5500 Dual Band 2 45GHz 5GHz Mini Chip Antenna from Johanson to use the same antenna across different designs The castellated PCB module has 137 castellated pads which are used for different volta...

Page 26: ...P8_0 P8_1 P6_5 P6_4 P6_7 P6_6 P6_LPO_IN P5_0 P5_1 P5_6 P5_7 P6_2 P9_1 P9_0 P10_0 P10_2 P10_1 P10_4 P10_3 P10_5 P11_0 P11_2 P11_1 P11_4 P11_3 P11_6 P11_5 P11_7 USBDP XRES_L USBDM PSoC 6 MCU Signals CY8C6245LQI S3D72 U1A P0 0 2 P0 1 3 P0 2 4 P0 3 5 P0 4 6 P0 5 7 P2 0 14 P2 1 15 P2 2 16 P2 3 17 P2 4 18 P2 5 19 P2 6 20 P2 7 21 P3 0 23 P3 1 24 P5 0 25 P5 1 26 P5 6 27 P5 7 28 P6 2 29 P6 3 30 P6 4 31 P6 ...

Page 27: ...ND11 45 GND12 46 GND_SR_PVSS1 32 GND_SR_PVSS2 33 L3 2 2uH C28 4 7uF 16V Supply for 1DX Module WL_JTAG_SEL BT_GPIO_4 BT_GPIO_3 BT_GPIO_5 WL_GPIO_4 EXT_LPO R35 0 OHM R34 0 OHM DNI LPO_OUT 1DX Module Signals LBEE5KL1DX 883 U2B WL_REG_ON 28 WL_HOST_WAKE 27 SDIO_CLK 20 SDIO_CMD 22 SDIO_DATA_0 24 SDIO_DATA_1 26 SDIO_DATA_2 23 SDIO_DATA_3 25 WL_GPIO_1 18 WL_GPIO_2 17 WL_GPIO_4 15 LPO_IN 37 ANT 41 BT_REG_...

Page 28: ... ARD_A1 60 ARD_A2 59 ARD_A3 58 ARD_A4 62 ARD_A5 63 ARD_A6 61 ARD_A7 64 ETM_CLK 44 ARD_A8 46 ARD_A9 48 ARD_A10 49 ARD_A11 45 ARD_A12 50 ARD_A13 56 ARD_A14 57 ARD_A15 51 ARD_D0 2 ARD_D1 3 ARD_D2 4 ARD_D3 6 ARD_D4 5 ARD_D5 9 ARD_D6 7 ARD_D7 8 ARD_D8 23 ARD_D9 25 ARD_D10 78 ARD_D11 76 ARD_D12 75 ARD_D13 77 I2C_SCL 136 I2C_SDA 133 CSX_TX 124 CSB_0 33 CSB_1 31 CSS_0 36 CSS_1 34 CSS_2 32 CSS_3 38 CSS_4 3...

Page 29: ...Load TP18 No Load UART_RX UART_TX P5LP_VDD VTARG_MEAS KP_DM KP_DP P5LP1_6 P5LP15_5 C12 1 0 uF No Load C13 1 0 uF R12 22E R15 0ohm C17 1 0 uF R11 22E U2 CY8C5868LTI LP039 P2 3 65 P2 1 63 P12 3 47 P3 7 37 P3 5 34 P3 3 32 P3 1 30 P15 3 41 P15 2 40 P1 7 19 P1 5 16 P1 3 14 P1 1 12 VSSD 25 P15 6 D 22 P15 7 D 23 VCCD 26 P12 0 38 P1 0 11 P1 2 13 P1 4 15 P1 6 18 P3 0 29 P3 2 31 P3 4 33 P12 1 39 P12 2 46 P3...

Page 30: ...remove R53 R64 R29 and R33 and then load R52 R63 R24 and R26 When connecting to BT UART directly using an external USB UART bridge or a KitProg3 that is separated from the board please ensure to connect VTARG to the level translator s input pin of the external USB UART bridge and GND to the corresponding ground pin of the external USB UART bridge This is to ensure proper level translation between ...

Page 31: ...ltage regulator and power selection circuits The voltage selection is made through jumper J3 Note VCC_3V3 can be optionally made to 2 5V for eFuse programming of PSoC 6 MCU by loading R20 Once completed it is expected that kit is reverted to 3 3V or 1 8V as operation of the board at 2 5V is not intended VCC_3V3 powers the Quad SPI flash that requires voltage 3 V and hence the flash will not functi...

Page 32: ...GND 2 IN 1 EN 3 PAD H VTARG C53 0 1uF 16V No Load VOUT R69 0ohm No Load R70 46 4K 1 U9 AP7365 WG 7 IN 1 GND 2 EN 3 ADJ 4 OUT 5 R66 57 6K 1 VCC_1V8 Voltage Regulator VCC_1V8 R62 62K VCC_3V6 R57 0ohm C40 4 7uF 10V C39 4 7uF 10V C50 0 1uF 16V C44 0 1uF 16V J3 TSW 103 08 F S RA 1 2 3 1 8V System Voltage Selection Header 3 3V VCC_3V3 VOUT VCC_1V8 ...

Page 33: ...rrent VBAT VDDIO_WL and P6_VDD It is recommended to supply external power in this scenario R54 0 OHM No Load Current Measurement VTARG P6_VDD VDDIO2 TP9 No Load R28 0 OHM R59 0 OHM VCC_3V6 VTARG VDDIO_WL VBAT_WL R55 0 OHM R71 0 OHM R51 0 OHM No Load P6_VDD VDDA VDDD P6_VDD VDD_NS FB3 1K FB1 1K FB2 1K VDDD VDDIO1 VBACKUP R58 0 OHM R25 0 OHM TP6 No Load TP11 No Load TP5 No Load TP12 No Load TP7 No L...

Page 34: ...wer Supply Pins Voltage Source Voltage Domain Device Power Pins Powered by Domain Operating Voltage Range Supported Voltage Voltage Selection Jumper Min V Max V VCC_3V6 VBAT_WL VBAT_WL 3 2 4 2 3 6V N A VTARG VDDIO_WL VDDIO2 VDDIO_WL 1 7 3 6 1 8V 3 3V J3 VTARG P6_VDD VDDD VDDIO0 VDDIO1 VDDA VDD_NS VBACKUP 1 7 3 6 1 8V 3 3V J3 VCC_3V3 VDD_USB VDD_USB 1 7 3 6 3 3V N A R28 R55 R59 R51 R71 R25 R46 R58 ...

Page 35: ...d U12 J6 and J7 are not loaded by default Figure 3 8 Schematics of PSoC 5LP GPIO Headers J6 and J7 P6_VDD VTARG VBAT_WL VBACKUP P6_VDD VREF I O Headers J1 CON 40x1 No Load 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J2 CON 40x1 No Load 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 3...

Page 36: ... PSoC 6 MCU respectively The board also has one user controllable LED LED4 connected to PSoC 6 MCU pin P11 1 for user applications Figure 3 10 Schematics of LEDs CS_CAP_SH CAP_SH1 SH 1 HATCH CapSense Shield R74 0 OHM R75 0 OHM No Load CS_TX_RX CapSense Header CS_SLD_2 CS_SLD_1 CS_SLD_0 CS_SLD_4 CS_SLD_3 CS_BTN_1 CS_BTN_0 CS_CAP_SH J4 CON 10X1 No Load 1 2 3 4 5 6 7 8 9 10 CS_TX_RX R83 2K No Load R7...

Page 37: ...nected to the Quad SPI interface of the PSoC 6 MCU The NOR device can be used for both data and code memory with execute in place XIP support and encryption Figure 3 12 Schematics of QSPI Flash 3 3 Bill of Materials Refer to the BOM files in the kit webpage SW2 SKRPACE010 1 4 2 3 USER_BTN_1 R48 10K VBACKUP User Button Hibernate Wakeup SW1 SKRPACE010 1 4 2 3 R56 4 7K No Load C46 0 1uF No Load XRES_...

Page 38: ...k J3 to ensure that a jumper shunt is placed b Make sure that no external devices are connected to J2 32 to J2 36 c Update your KitProg3 version to the latest version using the steps mentioned in the KitProg3 User Guide d Ensure that target device used in the IDE application is CY8C6245LQI S3D72 5 Does the kit get powered when I power the kit from another Cypress kit through the J9 header Yes VIN ...

Page 39: ...d Theory of Operation on page 16 Updated description Updated hyperlinks in required places Updated Figure 2 4 Updated KitProg3 On Board Programmer Debugger on page 20 Updated Programming and Debugging using ModusToolbox IDE on page 20 Updated Figure 2 5 Updated Using the OOB Example PSoC 6 MCU Hello World on page 23 Updated description added hyperlinks in required places Updated USB UART Bridge on...

Search results

Summary of Contents for CY8CPROTO-062S3-4343W

Reviews:

Related manuals for CY8CPROTO-062S3-4343W

Brands by name

Popular brands

Cypress CY8CPROTO-062S3-4343W, Manual

Search results

Summary of Contents for CY8CPROTO-062S3-4343W

Reviews:

Related manuals for CY8CPROTO-062S3-4343W

Brands by name

Popular brands