Cypress CY8C28 series, Technical Reference Manual

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CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G 321
Global Digital Interconnect (GDI)
14.1.4 48-Pin Global Interconnect
To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Charac-
teristics” on page 311 .
Figure 14-4. Global Interconnect Block Diagram for the CY8C286xx 48-Pin Package
P0[6]
GO
GI
P0[4]
GO
GI
P0[2]
GO
GI
P0[7]
GO
GI
P0[5]
GO
GI
P0[3]
GO
GI
P0[1]
GO
GI
P0[0]
GO
GI
P2[6]
GO
GI
P2[4]
GO
GI
P2[2]
GO
GI
P2[7]
GO
GI
P2[5]
GO
GI
P2[3]
GO
GI
P2[1]
GO
GI
P2[0]
GO
GI
P4[4]
GO
GI
P4[2]
GO
GI
P4[5]
GO
GI
P4[3]
GO
GI
P4[1]
GO
GI
P4[0]
GO
GI
P3[6]
GO
GI
P3[4]
GO
GI
P3[2]
GO
GI
P3[7]
GO
GI
P3[5]
GO
GI
P3[3]
GO
GI
P3[1]
GO
GI
P3[0]
GO
GI
P1[6]
GO
GI
P1[4]
GO
GI
P1[2]
GO
GI
P1[7]
GO
GI
P1[5]
GO
GI
P1[3]
GO
GI
P1[1]
GO
GI
P1[0]
GO
GI
GI
E[
0]
GI
E[
2]
GI
E[
4]
GI
E[
6]
GO
E[0
]
GO
E[2
]
GO
E[4
]
GO
E[6
]
GO
E[7]
GO
E[5]
GO
E[3]
GO
E[1]
GI
E[
7]
GI
E[
5]
GI
E[
3]
GI
E[
1]
GI
O
[0]
GI
O
[2]
GI
O
[4]
GI
O
[6]
GO
O[
0]
GO
O[
2]
GO
O[
4]
GO
O[
6]
GO
O[
7]
GO
O[
5]
GO
O[
3]
GO
O[
1]
GI
O
[7]
GI
O
[5]
GI
O
[3]
GI
O
[1]
Even Numbered Pins
Odd Numbered Pins
GIO[7,5,3,1]
GIE[7,5,3,1]
DB[7
:0
]
DB
I
IN
T[
23
:8
]
CL
K3
2K
VC
3
ACM
P[3
:0
]
SY
SC
LK
X2
VC
2
VC
1
GIO[6,4,2,0]
GIE[6,4,2,0]
GOO[7,5,3,1]
GOE[7,5,3,1]
GOO[6,4,2,0]
GOE[6,4,2,0]
Digital PSoC Array
SYSCLKX2 SYSCLK
CLK32K
Digital Clocks
VC3
VC1 VC2
Odd
Numbered
Ports
Even
Numbered
Ports
SLPINT
CLK24M
Even Numbered Pins
Odd Numbered Pins
GOO[0]
GOO[2]
GOO[4]
GOO[6]
GIO[1]
GIO[3]
GIO[5]
GIO[7]
GIO[0]
GIO[2]
GIO[4]
GIO[6]
GOO[1]
GOO[3]
GOO[5]
GOO[7]
GOE[0]
GOE[2]
GOE[4]
GOE[6]
GIE[1]
GIE[3]
GIE[5]
GIE[7]
GIE[0]
GIE[2]
GIE[4]
GIE[6]
GOE[1]
GOE[3]
GOE[5]
GOE[7]
CY8C28xxx Type-E Column
AEC1 AEC0
CY8C28xxx Analog Array
ACC Comp
Bus 1
ACC Comp
Bus 0
ACC Comp
Bus 3
ACC Comp
Bus 2
P4[7]
GO
GI
P4[6]
GO
GI
P5[2]
GO
GI
P5[0]
GO
GI
P5[3]
GO
GI
P5[1]
GO
GI