CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
211
RES_WDT
0,E3h
13.2.76
RES_WDT
Reset Watchdog Timer Register
This register is used to clear the watchdog timer and clear both the watchdog timer and the sleep timer.
For additional information, refer to the
“Register Definitions” on page 99
in the Sleep and Watchdog chapter.
7:0
WDSL_Clear[7:0]
Any write clears the watchdog timer. A write of 38h clears both the watchdog and sleep timers.
Individual Register Names and Addresses:
0,E3h
RES_WDT: 0,E3h
7
6
5
4
3
2
1
0
Access : POR
W : 00
Bit Name
WDSL_Clear[7:0]
Bit
Name
Description
Summary of Contents for CY8C28 series
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