CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
207
INT_MSK2
0,DFh
13.2.72
INT_MSK2
Interrupt Mask Register 2
This register is used to enable the individual sources’ ability to create pending interrupts for digital blocks.
When an interrupt is masked off in this register, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. There-
fore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. In the table, note that reserved
bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a
value of ‘0’. For additional information, refer to the
“Register Definitions” on page 68
in the Interrupt Controller chapter.
3
DCC23
0
Mask Digital Communication Block, row 2, position 3 interrupt.
1
Unmask Digital Communication Block, row 2, position 3 interrupt.
2
DCC22
0
Mask Digital Communication Block, row 2, position 2 interrupt.
1
Unmask Digital Communication Block, row 2, position 2 interrupt.
1
DBC21
0
Mask Digital Basic Block, row 2, position 1 interrupt.
1
Unmask Digital Basic Block, row 2, position 1 interrupt.
0
DBC20
0
Mask Digital Basic Block, row 2, position 0 interrupt.
1
Unmask Digital Basic Block, row 2, position 0 interrupt.
Individual Register Names and Addresses:
0,DFh
INT_MSK2: 0,DFh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
DCC23
DCC22
DBC21
DBC20
Bit
Name
Description
Summary of Contents for CY8C28 series
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