SADC_DL
154
CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
0,6Bh
13.2.26
SADC_DL
SAR ADC Data Low Register
The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45
PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information,
in the 10-Bit SAR ADC Controller chapter.
7:0
Data Low [7:0]
The low byte of ADC data. It contains the least significant 8 bits of the 10-bit sample in right-justified
data format. In left-justified data format only the bits [1:0] are valid to hold the least significant 2 bits of
the 10-bit sample.
Individual Register Names and Addresses:
0,6Bh
SADC_DL : 0,6Bh
7 6 5 4 3 2 1 0
Access : POR
R : 00
Bit Name
Data Low [7:0]
Bit
Name
Description
Summary of Contents for CY8C28 series
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