Cypress CY62157EV18 Specification Sheet Download

Page: 7 / 12

CY62157EV18 MoBL

Document #: 38-05490 Rev. *D

Page 7 of 12

Write Cycle 1

(WE Controlled)

[16, 20, 21]

Write Cycle 2

(CE

or CE

Controlled)

[16, 20, 21]

Switching Waveforms

(continued)

PWE

SCE

HZOE

VALID DATA

NOTE 22

ADDRESS

DATA IO

BHE/BLE

PWE

SCE

HZOE

VALID DATA

NOTE 22

ADDRESS

DATA IO

BHE/BLE

Notes:

20. Data IO is high impedance if OE = V

21. If CE

goes HIGH and CE

goes LOW simultaneously with WE = V

, the output remains in a high impedance state.

22. During this period, the IOs are in output state and input signals must not be applied.

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Summary of Contents for CY62157EV18

Page 1: ...1 HIGH or CE2 LOW Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or Write operation is active CE1 LOW CE2 HIGH and WE LOW Write to the device by taking Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW If Byte Low Enable BLE is LOW then data from IO pins IO0 through IO7 is written into the location specified on the address pins A0 thr...

Page 2: ...DATA IN DRIVERS OE A4 A3 IO8 IO15 WE BLE BHE A 16 A0 A1 A 17 A9 BHE BLE A10 A 18 POWER DOWN CIRCUIT CE2 CE1 CE2 CE1 Note 3 NC pins are not connected on the die WE A11 A10 A6 A0 A3 CE1 IO10 IO8 IO9 A4 A5 IO11 IO13 IO12 IO14 IO15 VSS A9 A8 OE A7 IO0 BHE CE2 A17 A2 A1 BLE IO2 IO1 IO3 IO4 IO5 IO6 IO7 A15 A14 A13 A12 NC A18 NC 3 2 6 5 4 1 D E B A C F G H A16 NC VCC VCC VSS 48 ball VFBGA Top View Feedba...

Page 3: ...IL Input LOW Voltage VCC 1 65V to 2 25V 0 2 0 4 V IIX Input Leakage Current GND VI VCC 1 1 µA IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 µA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCC max IOUT 0 mA CMOS levels 18 25 mA f 1 MHz 1 8 3 mA ISB1 Automatic CEPower Down Current CMOS Inputs CE1 VCC 0 2V or CE2 0 2V VIN VCC 0 2V VIN 0 2V f fmax Address and Data Only f 0 OE WE BHE a...

Page 4: ...tention 1 0 V ICCDR Data Retention Current VCC VDR CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V 1 3 µA tCDR 8 Chip Deselect to Data Retention Time 0 ns tR 9 Operation Recovery Time tRC ns Data Retention Waveform 10 3V VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1 V ns Fall Time 1 V ns OUTPUT V Equivalent to THEVENIN EQUIVALENT ALL INPUT PULSES RTH R1 VCC min tCDR VDR 1 ...

Page 5: ...te End 0 ns tHZWE WE LOW to High Z 13 14 18 ns tLZWE WE HIGH to Low Z 13 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 1V ns or less timing reference levels of VCC typ 2 input pulse levels of 0 to VCC typ and output loading of the specified IOL IOH as shown in the AC Test Loads and Waveforms on page 4 12 AC timing parameters are ...

Page 6: ... ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZBE tLZBE tHZCE tDBE OE CE1 ADDRESS CE2 BHE BLE DATA OUT VCC SUPPLY CURRENT HIGH ICC ISB IMPEDANCE Notes 17 The device is continuously selected OE CE1 VIL BHE and or BLE VIL and CE2 VIH 18 WE is HIGH for read cycle 19 Address valid before or similar to CE1 BHE BLE transition LOW and CE2 transition HIGH Feed...

Page 7: ...LID DATA tBW NOTE 22 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE VALID DATA tBW tSA NOTE 22 CE1 ADDRESS CE2 WE DATA IO OE BHE BLE Notes 20 Data IO is high impedance if OE VIH 21 If CE1 goes HIGH and CE2 goes LOW simultaneously with WE VIH the output remains in a high impedance state 22 During this period the IOs are in output state and input signals must not be applie...

Page 8: ... LOW 21 Write Cycle 4 BHE BLE Controlled OE LOW 21 Switching Waveforms continued VALID DATA tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 22 CE1 ADDRESS CE2 WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC VALID DATA tBW tSCE tPWE NOTE 22 CE1 ADDRESS CE2 WE DATA IO BHE BLE Feedback ...

Page 9: ...a Out IO8 IO15 Read Active ICC L H H H L H High Z Output Disabled Active ICC L H H H H L High Z Output Disabled Active ICC L H H H L L High Z Output Disabled Active ICC L H L X L L Data In IO0 IO15 Write Active ICC L H L X H L Data In IO0 IO7 High Z IO8 IO15 Write Active ICC L H L X L H High Z IO0 IO7 Data In IO8 IO15 Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Pac...

Page 10: ...e a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges CY62157EV18 MoBL Package Diagrams Figure 1 48 ball VFBGA 6 x 8 x 1 mm 51 85150 MoBL is a registered trademark and Mor...

Page 11: ... ns Speed Bins respectively Added Pb Free Package Information B 444306 See ECN NXR Converted from Preliminary to Final Removed 35 ns speed bin Removed L bin Changed ball E3 from DNU to NC Removed redundant footnote on DNU Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2 4V to 2 45V Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for t...

Page 12: ...2 D 908120 See ECN VKN Added footnote 7 related to ISB2 Added footnote 12 related AC timing parameters Document Title CY62157EV18 MoBL 8 Mbit 512K x 16 Static RAM Document Number 38 05490 REV ECN NO Issue Date Orig of Change Description of Change Feedback ...

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