Cypress CY14B108K Specification Sheet Download | Manualshive

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PRELIMINARY

CY14B108K, CY14B108M

Document #: 001-47378 Rev. **

Page 25 of 29

Part Numbering Nomenclature

Option:
T - Tape & Reel
Blank - Std.

Speed:

20 - 20 ns
25 - 25 ns

Data Bus:
K - x8 + RTC
M - x16 + RTC

Density:

108 - 8 Mb

Voltage:
B - 3.0V

Cypress

CY14 B 108 K ZS P 20 X C T

NVSRAM

14 - Aut Software STORE + Hardware STORE

Temperature:

C - Commercial (0 to 70°C)

I - Industrial (–40 to 85°C)

Pb-Free

Package:

ZS - TSOP II

P - 54 Pin
Blank - 44 Pin

45 - 45 ns

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Summary of Contents for CY14B108K

Page 1: ...le static RAM with a full featured RTC in a monolithic integrated circuit The embedded nonvolatile elements incor porate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM is read and written infinite number of times while independent nonvolatile data resides in the nonvolatile elements The RTC function provides an accurate clock with leap year tracking and a pr...

Page 2: ...o tri state BHE Input Byte High Enable Active LOW Controls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 Xout Output Crystal Connection Drives crystal on start up Xin Input Crystal Connection For 32 768 KHz crystal VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage Left unconnected if VRTCbat is used VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage Le...

Page 3: ...bit words Keep OE HIGH during the entire write cycle to avoid data bus contention on common I O lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation The CY14B108K CY14B108M stores data to the nvSRAM using one of three storage operations These three operations are Hardware STORE activated by the HSB Software STORE activated by an addres...

Page 4: ...n is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The CY14B108K CY14B108M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previou...

Page 5: ...hrough subsequent power down cycles The part comes from the factory with AutoStore enabled Table 2 Mode Selection CE WE OE BHE BLE 3 A15 A0 5 Mode I O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Dat...

Page 6: ...ating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot status and so on should always program a unique NV pattern that is complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufac turing t...

Page 7: ...r to 0x0 after which RTC resumes normal operation Note The values entered in the timekeeping alarm calibration and interrupt registers need a STORE operation to be saved in nonvolatile memory Therefore while working in AutoStore disabled mode the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly Backup Power The RTC in the CY14B108K is intended ...

Page 8: ...ate stored in the registers 0xFFFF1 5 with the corre sponding time of day and date values When a match occurs the alarm internal flag AF is set and an interrupt is generated on INT pin if Alarm Interrupt Enable AIE bit is set There are four alarm match fields date hours minutes and seconds Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic ...

Page 9: ... are only generated while working on normal power and are not triggered when system is running in backup power mode Note CY14B108K generates valid interrupts only after the Powerup Recall sequence is completed All events on INT pin must be ignored for tHRECALL duration after powerup Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin and an internal...

Page 10: ... pF C1 21 pF C2 21 pF Note The recommended values for C1 and C2 include board trace capacitance Xout Xin Y1 C2 C1 Watchdog Timer Power Monitor Clock Alarm VINT WDF WIE PF PFE AF AIE P L Pin Driver H L INT VCC VSS WDF Watchdog Timer Flag WIE Watchdog Interrupt PF Power Fail Flag PFE Power Fail Enable AF Alarm Flag AIE Alarm Interrupt Enable P L Pulse Level H L High Low Enable Feedback ...

Page 11: ...xFFFF8 0x7FFF8 OSCEN 0 0 Cal Sign 0 Calibration 00000 Calibration Values 9 0xFFFF7 0x7FFF7 WDS 0 WDW 0 WDT 000000 Watchdog 9 0xFFFF6 0x7FFF6 WIE 0 AIE 0 PFE 0 0 H L 1 P L 0 0 0 Interrupts 9 0xFFFF5 0x7FFF5 M 1 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 0xFFFF4 0x7FFF4 M 1 0 10s Alarm Hours Alarm Hours Alarm Hours 00 23 0xFFFF3 0x7FFF3 M 1 10 Alarm Minutes Alarm Minutes Alarm Minutes 00 59...

Page 12: ...tomatically adjusted for 0xFFFFC 0x7FFFC Time Keeping Day D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day of Week Lower nibble three bits contains a value that correlates to day of the week Day of the week is a ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value because the day is not integrated with the date 0xFFFFB 0x7FFFB Time Keeping Hours D7 D6 D5 D4 D3 ...

Page 13: ...tiplier of the 32 Hz count 31 25 ms The range of timeout value is 31 25 ms a setting of 1 to 2 seconds setting of 3 Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was set to 0 on a previous cycle 0xFFFF6 0x7FFF6 Interrupt Status Control D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFE 0 H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a w...

Page 14: ...atchdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up PF Power Fail Flag This read only bit is set to 1 when power falls b...

Page 15: ...rial 75 75 57 mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 20 mA ICC3 10 Average VCC Current at tRC 200 ns 3V 25 C typical All Inputs Cycling at CMOS Levels Values obtained without output loads IOUT 0 mA 40 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ISB ...

Page 16: ...t CIN Input Capacitance TA 25 C f 1 MHz VCC 0 to 3 0V 14 pF COUT Output Capacitance 14 pF Thermal Resistance In the following table the thermal resistance parameters are listed 13 Parameter Description Test Conditions 44 TSOP II 54 TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Test conditionsfollow standard test methods and procedures for measuring thermal impedance in accordance with EI...

Page 17: ...cription Test Conditions Min Typ Max Units IBAK 14 RTC Backup Current Room Temperature 25o C 300 nA Hot Temperature 85o C 450 nA VRTCbat RTC Battery Pin Voltage 1 8 3 0 3 3 V VRTCcap RTC Capacitor Pin Voltage 1 5 3 0 3 6 V tOCS RTC Oscillator Time to Start 1 2 sec Note 14 From either VRTCcap or VRTCbat Feedback ...

Page 18: ... 0 ns tHZBE 13 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tWR A...

Page 19: ...20 Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE BHE BLE ICC tHZCE tRC tACE tAA tLZCE tDOE tLZOE tDBE tLZBE tPU tPD tHZBE tHZOE Data Output Data Input Input Data Valid High Impedance Address Valid Address Previous Data tWC tSCE tHA tBW tAW tPWE tSA tSD tHD tHZWE tLZWE WE BHE BLE CE Note 20 CE or WE must be VIH during address transitions Feedback ...

Page 20: ...t Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSCE tSA tBW tHA tAW tPWE Not applicable for RTC register writes Note 21 Only CE and WE controlled writes to RTC registers are allowed BLE pin must be held LOW before CE or WE pin goes LOW for ...

Page 21: ... RECALL 25 VSWITCH VHDIS VVCCRISE tSTORE tSTORE tHHHD tHHHD tDELAY tDELAY tLZHSB tLZHSB tHRECALL tHRECALL HSB OUT Autostore POWER UP RECALL Read Write Inhibited RWI POWER UP RECALL Read Write BROWN OUT Autostore POWER UP RECALL Read Write POWER DOWN Autostore Note23 Note23 Note26 Notes 22 tHRECALL starts from the time VCC rises above VSWITCH 23 If an SRAM write has not taken place since the last n...

Page 22: ...Figure 14 AutoStore Enable and Disable Cycle tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY tSTORE tRECALL tHHHD tLZHSB High Impedance Address 1 Address 6 Address CE OE HSB STORE only DQ DATA RWI tRC tRC tSA tCW tCW tSA tHA tLZCE tHZCE tHA tHA tHA tDELAY Address 1 Address 6 Address CE OE DQ DATA tSS Notes 27 The software sequence is clocked with CE controlled or OE controlled reads 28 ...

Page 23: ...tch set Write latch not set HSB IN HSB OUT DQ Data Out RWI HSB IN HSB OUT RWI HSB pin is driven high to VCC only by Internal SRAM is disabled as long as HSB IN is driven low HSB driver is disabled tDHSB 100kOhm resistor Address 1 Address 6 Address 1 Address 6 Soft Sequence Command tSS tSS CE Address VCC tSA tCW Soft Sequence Command tCW Notes 31 This is the amount of time it takes to take action o...

Page 24: ...E WE OE BHE 3 BLE 3 Inputs and Outputs 2 Mode Power H X X X X High Z Deselect Power Down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Dis...

Page 25: ...e Reel Blank Std Speed 20 20 ns 25 25 ns Data Bus K x8 RTC M x16 RTC Density 108 8 Mb Voltage B 3 0V Cypress CY14 B 108 K ZS P 20 X C T NVSRAM 14 AutoStore Software STORE Hardware STORE Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Pb Free Package ZS TSOP II P 54 Pin Blank 44 Pin 45 45 ns Feedback ...

Page 26: ... TSOPII CY14B108K ZS25XIT 51 85087 44 pin TSOPII Industrial CY14B108K ZS25XI 51 85187 44 pin TSOPII CY14B108M ZSP25XCT 51 85160 54 pin TSOPII Commercial CY14B108M ZSP25XC 51 85160 54 pin TSOPII CY14B108M ZSP25XIT 51 85160 54 pin TSOPII Industrial CY14B108M ZSP25XI 51 85160 54 pin TSOPII 45 CY14B108K ZS45XCT 51 85087 44 pin TSOPII Commercial CY14B108K ZS45XC 51 85087 44 pin TSOPII CY14B108K ZS45XIT...

Page 27: ... PLANE SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Page 28: ...PRELIMINARY CY14B108K CY14B108M Document 001 47378 Rev Page 28 of 29 Figure 18 54 Pin TSOP II 51 85160 Package Diagrams continued 51 85160 Feedback ...

Page 29: ...in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PART...

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