Cypress CY14B104L Specification Sheet Download | Manualshive

Page: 10 / 25

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CY14B104L, CY14B104N

Document #: 001-07102 Rev. *L

Page 10 of 25

Figure 7. SRAM Read Cycle #2: CE and OE Controlled

[3, 14, 18]

Figure 8. SRAM Write Cycle #1: WE Controlled

[3, 17, 18, 19]

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Notes

19. CE or WE must be >V

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during address transitions.

[+] Feedback

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Summary of Contents for CY14B104L

Page 1: ...le element in each memory cell The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM t...

Page 2: ...for 8 Mbit NC pin not connected to die 5 Address expansion for 16 Mbit NC pin not connected to die 6 HSB pin is not available in 44 TSOP II x16 package NC A8 NC NC VSS DQ6 DQ5 DQ4 VCC A13 DQ3 A12 DQ2 DQ1 DQ0 OE A9 CE NC A0 A1 A2 A3 A4 A5 A6 A11 A7 A14 A15 A16 A17 A18 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 TSO...

Page 3: ...ls DQ15 DQ8 BLE Input Byte Low Enable Active LOW Controls DQ7 DQ0 VSS Ground Ground for the Device Must be connected to the ground of the system VCC Power Supply Power Supply Inputs to the Device HSB 6 Input Output Hardware Store Busy HSB When LOW this output indicates that a hardware store is in progress When pulled LOW external to the chip it initiates a nonvolatile STORE operation A weak intern...

Page 4: ...d by HSB Software Store activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104L CY14B104N During a normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the...

Page 5: ...B will be driven LOW It is important to use read cycles and not write cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the tSTORE cycle time is fulfilled the SRAM is activated again for the read and write operation Software RECALL Transfer the data from the nonvolatile memory to the SRAM with a software address sequence A software RECALL cycle is initia...

Page 6: ... be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Data Protection The CY14B104L CY14B104N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when VCC VSWITCH If the CY14B104L CY14B104N is in a write mode bo...

Page 7: ... 70 52 mA mA mA ICC2 Average VCC Current during STORE All Inputs Don t Care VCC Max Average current for duration tSTORE 10 mA ICC3 10 AverageVCC Currentat tRC 200 ns 3V 25 C typical All inputs cycling at CMOS levels Values obtained without output loads IOUT 0 mA 35 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Don t Care VCC Max Average current for duration tSTORE 5 mA ISB VCC Sta...

Page 8: ...acitance TA 25 C f 1 MHz VCC 0 to 3 0V 7 pF COUT Output Capacitance 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 13 Parameter Description Test Conditions 48 FBGA 44 TSOP II 54 TSOP II Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51...

Page 9: ...ns tHZBE Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable To End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to Start of Write 0 0 0 ns tHA tWR Address...

Page 10: ...RAM Write Cycle 1 WE Controlled 3 17 18 19 GGUHVV 9DOLG GGUHVV DWD 2XWSXW 2XWSXW DWD 9DOLG 6WDQGE FWLYH LJK PSHGDQFH 2 W W5 W W W W 2 W 2 W W W38 W3 W W 2 DWD 2XWSXW DWD QSXW QSXW DWD 9DOLG LJK PSHGDQFH GGUHVV 9DOLG GGUHVV 3UHYLRXV DWD W W6 W W W W3 W6 W6 W W W Notes 19 CE or WE must be VIH during address transitions Feedback ...

Page 11: ...ed 3 17 18 19 Figure 10 SRAM Write Cycle 3 BHE and BLE Controlled 3 17 18 19 Data Output Data Input Input Data Valid High Impedance Address Valid Address tWC tSD tHD BHE BLE WE CE tSA tSCE tHA tBW tPWE DWD 2XWSXW DWD QSXW QSXW DWD 9DOLG LJK PSHGDQFH GGUHVV 9DOLG GGUHVV W W6 W W6 W6 W W W W3 Feedback ...

Page 12: ...11 AutoStore or Power Up RECALL 23 W6725 9 96 7 W9 5 6 W6725 XWR6WRUH 32 5 83 5 W 5 W 5 5HDG ULWH QKLELWHG 32 5 83 5 5HDG ULWH 52 1 287 XWR6WRUH 32 5 83 5 5HDG ULWH 32 5 2 1 XWR6WRUH 1RWH 6 9 6 95 6 7 1RWH W W W 6 W 6 287 W385 W W 1RWH Notes 20 tHRECALL starts from the time VCC rises above VSWITCH 21 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware Sto...

Page 13: ...0 100 μs Switching Waveforms Figure 12 CE and OE Controlled Software STORE RECALL Cycle 26 Figure 13 Autostore Enable Disable Cycle W5 W5 W6 W W W6 W W W W W W W6725 W5 W W 6 LJK PSHGDQFH GGUHVV GGUHVV GGUHVV 2 6 6725 RQO 4 7 5 W66 W W5 W5 W6 W W W6 W W W W W W W GGUHVV GGUHVV GGUHVV 2 4 7 5 W66 Notes 25 The software sequence is clocked with CE controlled or OE controlled reads 26 The six consecut...

Page 14: ...ssing 27 28 W3 6 W3 6 W W6725 W W 6 ULWH ODWFK VHW ULWH ODWFK QRW VHW 6 1 6 287 4 DWD 2XW 6 1 W W W W 6 6 287 4 DWD 2XW W GGUHVV GGUHVV GGUHVV GGUHVV 6RIW 6HTXHQFH RPPDQG W66 W66 GGUHVV 9 W6 W 6RIW 6HTXHQFH RPPDQG W Notes 27 This is the amount of time it takes to take action on a soft sequence command VCC power must remain HIGH to effectively register command 28 Commands such as STORE and RECALL l...

Page 15: ...E OE BHE BLE Inputs Outputs 2 Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQ0 DQ15 Read Active L H L H L Data Out DQ0 DQ7 DQ8 DQ15 in High Z Read Active L H L L H Data Out DQ8 DQ15 DQ0 DQ7 in High Z Read Active L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabled Activ...

Page 16: ...1 85128 48 ball FBGA CY14B104N ZSP20XCT 51 85160 54 pin TSOP II Commercial CY14B104N ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14B104N ZSP20XI 51 85160 54 pin TSOP II 25 CY14B104L ZS25XCT 51 85087 44 pin TSOP II Commercial CY14B104L ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B104L ZS25XI 51 85087 44 pin TSOP II CY14B104L BA25XIT 51 85128 48 ball FBGA Industrial CY14B104L BA25XI 51 85128 48...

Page 17: ...Y14B104N ZS45XCT 51 85087 44 pin TSOP II Commercial CY14B104N ZS45XIT 51 85087 44 pin TSOP II Industrial CY14B104N ZS45XI 51 85087 44 pin TSOP II CY14B104N BA45XCT 51 85128 48 ball FBGA Commercial CY14B104N BA45XIT 51 85128 48 ball FBGA Industrial CY14B104N BA45XI 51 85128 48 ball FBGA CY14B104N ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14B104N ZSP45XIT 51 85160 54 pin TSOP II Industrial CY14B...

Page 18: ...lank Std Speed 20 20 ns 25 25 ns Data Bus L x8 N x16 Density 104 4 Mb Voltage B 3 0V Cypress CY 14 B 104 L ZS P 20 X C T NVSRAM 14 Auto Store Software Store Hardware Store Temperature C Commercial 0 to 70 C I Industrial 40 to 85 C Pb Free Package BA 48 FBGA ZS TSOP II P 54 Pin Blank 44 Pin 45 45 ns Feedback ...

Page 19: ...E SEATING PIN 1 I D 44 1 18 517 0 729 0 800 BSC 0 5 0 400 0 016 0 300 0 012 EJECTOR PIN R G O K E A X S 11 735 0 462 10 058 0 396 10 262 0 404 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 0 0315 18 313 0 721 10 058 0 396 10 262 0 404 0 597 0 0235 0 406 0 0160 0 210 0 0083 0 120 0 0047 BASE PLANE 0 10 004 22 23 TOP VIEW BOTTOM VIEW 51 85087 A Feedback ...

Page 20: ...grams continued A 1 A1 CORNER 0 75 0 75 Ø0 30 0 05 48X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 21 0 05 1 20 MAX C SEATING PLANE 0 53 0 05 0 25 C 0 15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H 6 5 4 6 5 2 3 1 D H F G E C B A 6 00 0 10 10 00 0 10 A 10 00 0 10 6 00 0 10 B 1 875 2 625 0 36 51 85128 D Feedback ...

Page 21: ...CY14B104L CY14B104N Document 001 07102 Rev L Page 21 of 25 Figure 18 54 Pin TSOP II 51 85160 Package Diagrams continued 51 85160 Feedback ...

Page 22: ...ormation table C 517793 See ECN TUP Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35μF Changed VIH max to Vcc 0 5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE tDBE tLZBE tHZBE tBW Removed min specific...

Page 23: ...e from 22 ns to 15 ns for 45 ns part Corrected typo in tAW value from 15 ns to 10ns for 15 ns part Changed tRECALL from 100 to 200 us Added footnotes 9 and 25 Reframed footnote 14 and 21 Added footnote 14 to figure 7 SRAM WRITE Cycle 1 H 2483627 See ECN GVCH PYRS Removed 8 mA typical ICC at 200 ns cycle time in Feature section Referenced footnote 8 to ICC3 in DC Characteristics table Changed ICC3 ...

Page 24: ...anged tDELAY to 20ns 25ns 25ns for 15ns 20ns 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS tHHHD and tLZHSB parameters Updated footnote 21 Added footnote 24 Software controlled STORE RECALL cycle table Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering inform...

Page 25: ...or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED W...

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