Cypress CE219490, User Manual

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PSoC 6 MCU Ramping LED using Smart I/O
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Document No. 002-25568 Rev.*A 6
Table 3. Smart I/O LUT Configuration
LUT# Mode LUT inputs LUT
Output
Mapping
Description
TR2 TR1 TR0
LUT2 Sequential (gated) output LUT2 LUT2 LUT2 0x01 Implements a logic NOT operation
LUT3 Sequential (gated) output LUT3 LUT3 LUT2 0x81 Implements a logic XNOR operation
LUT4 Combinatorial output LUT3 LUT3 Chip 4 0x42 Implements a logic XOR operation
Figure 6 and Figure 7 show the Peripheral-Clock configuration for Smart I/O and TCPWM resources respectively.
Figure 6. Peripheral-Clock Configuration for Smart I/O
Figure 7. Peripheral-Clock Configuration for TCPWM
Reusing This Example
This example is designed for the supported kits . To port the design to a different PSoC 6 MCU device, right-click an application
project and choose Change Device . If changing to a different kit, you may need to reassign pins.
Table 4. Device and Pin Mapping Table across PSoC 6 MCU Kits
Kit Name Device Used LED
CY8CKIT-062-BLE CY8C6347BZI-BLD53 P13[7]
CY8CKIT-062-WiFi-BT CY8C6247BZI-D54 P13[7]
CY8CPROTO-062-4343W CY8C624ABZI-D44 P13[7]