Cypress CapSense CY8C20396 Specification Sheet Download

Page: 32 / 34

CY8C20x36/46/66, CY8C20396

Document Number: 001-12696 Rev. *D

Page 32 of 34

Ordering Information

The following table lists the CY8C20x36/46/66, CY8C20396 PSoC devices key package features and ordering codes.

Table 36. PSoC Device Key Features and Ordering Information

Package

Ordering Code

Flash

(Bytes)

SRAM

(Bytes)

CapSense

Blocks

Digital IO

Pins

Analog

Inputs

XRES

Pin

USB

16-Pin (3x3x0.6mm) QFN

CY8C20236-24LKXI

Yes

16-Pin (3x3x0.6mm) QFN
(Tape and Reel)

CY8C20236-24LKXIT

Yes

24-Pin (4x4x0.6mm) QFN

CY8C20336-24LQXI

Yes

24-Pin (4x4x0.6mm) QFN
(Tape and Reel)

CY8C20336-24LQXIT

Yes

32-Pin (5x5x0.6mm) QFN

CY8C20436-24LQXI

Yes

32-Pin (5x5x0.6mm) QFN
(Tape and Reel)

CY8C20436-24LQXIT

Yes

24-Pin (4x4x0.6mm) QFN

CY8C20396-24LQXI

16K

Yes

24-Pin (4x4x0.6mm) QFN
(Tape and Reel)

CY8C20396-24LQXIT

16K

Yes

16 Pin (3x3 x 0.6 mm) QFN

CY8C20246-24LKXI

16K

2048

[17]

Yes

16 Pin (3x3 x 0.6 mm) QFN
(Tape and Reel)

CY8C20246-24LKXIT

16K

2048

[17]

Yes

24 Pin (4x4 x 0.6 mm) QFN

CY8C20346-24LQXI

16K

2048

[17]

Yes

24 Pin (4x4 x 0.6 mm) QFN
(Tape and Reel)

CY8C20346-24LQXIT

16K

2048

[17]

Yes

32 Pin (5x5 x 0.6 mm) QFN

CY8C20446-24LQXI

16K

2048

[17]

Yes

32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)

CY8C20446-24LQXIT

16K

2048

[17]

Yes

32 Pin (5x5 x 0.6 mm) QFN

CY8C20466-24LQXI

32K

2048

[17]

Yes

32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)

CY8C20466-24LQXIT

32K

2048

[17]

Yes

48-Pin SSOP

CY8C20566-24PVXI

32K

2048

[17]

Yes

48-Pin SSOP
(Tape and Reel)

CY8C20566-24PVXIT

32K

2048

[17]

Yes

48 Pin (7x7 mm) QFN

CY8C20666-24LTXI

32K

2048

[17]

Yes

48 Pin (7x7 mm) QFN
(Tape and Reel)

CY8C20666-24LTXIT

32K

2048

[17]

Yes

48 Pin (7x7 mm) QFN (OCD)

[4]

CY8C20066-24LTXI

32K

2048

[17]

Yes

Notes

17. Dual-function Digital IO Pins also connect to the common analog mux.

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Summary of Contents for CapSense CY8C20396

Page 1: ...20666 only Programmable Pin Configurations Up to 36 GPIO Depending on Package Dual Mode GPIO All GPIO Support Digital IO and Analog Input 25 mA Sink Current on All GPIO Pull up High Z Open Drain Modes on All GPIO CMOS Drive Mode 5 mA Source Current on Ports 0 and 1 20 mA at 3 0V Total Source Current on Port 0 20 mA at 3 0V Total Source Current on Port 1 Selectable Regulated Digital IO on Port 1 Co...

Page 2: ...ain Oscillator IMO PSoC CORE CPU Core M8C Supervisory ROM SROM 8K 16K 32K Flash Nonvolatile Memory SYSTEM RESOURCES SYSTEM BUS Analog Reference SYSTEM BUS Port 3 Port 2 Port 1 Port 0 CapSense Module Global Analog Interconnect 1 8 2 5 3V LDO Analog Mux Two Comparators I2C Slave SPI Master Slave POR and LVD USB System Resets Internal Voltage References Three 16 Bit Programmable Timers PWRSYS Regulat...

Page 3: ...tional capability such as configurable USB and I2C slave SPI master slave communication interface three 16 bit programmable timers and various system resets supported by the M8C The Analog System is composed of the CapSense PSoC block and an internal 1 2V analog reference which together support capacitive sensing of up to 36 inputs CapSense Analog System The Analog System contains the capacitive s...

Page 4: ...y connector Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment IDE This data sheet is an overview of the PSoC integrated circuit and presents specific pin register and electrical specifications For in depth information along with detailed programming details see the PSoC Programmable System on Chi...

Page 5: ...chip level view to gain complete control over on chip resources All views of the project share common code editor builder and common debug emulation and programming tools Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools T...

Page 6: ... and other information you may need to successfully implement your design Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the IO pins or connect system level inputs outputs and communication interfaces to each other with valuator functions In the system level view selecting a potentiometer driver to control a variable speed fan drive...

Page 7: ...e represented by a 0x prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not indicated by an h b or 0x are decimal Table 1 Acronyms Acronym Description AC alternating current API application programming interface CPU central processing unit DC direct current FSR full scale range GPIO general purpose IO GUI graphical user interface ...

Page 8: ...LK 1 I2C SCL SPI MOSI 7 Power Vss Ground connection 8 IOHR I P1 0 ISSP DATA 1 I2C SDA SPI CLK 9 IOHR I P1 2 10 IOHR I P1 4 Optional external clock EXTCLK 11 Input XRES Active high external reset with internal pull down 12 IOH I P0 4 13 Power Vdd Supply voltage 14 IOH I P0 7 15 IOH I P0 3 Integrating input 16 IOH I P0 1 Integrating input LEGEND A Analog I Input O Output OH 5 mA High Output Drive R ...

Page 9: ...onnection 10 IOHR I P1 0 ISSP DATA 1 I2C SDA SPI CLK 11 IOHR I P1 2 12 IOHR I P1 4 Optional external clock input EXTCLK 13 IOHR I P1 6 14 Input XRES Active high external reset with internal pull down 15 IO I P2 0 16 IOH I P0 0 17 IOH I P0 2 18 IOH I P0 4 19 IOH I P0 6 20 Power Vdd Supply voltage 21 IOH I P0 7 22 IOH I P0 5 23 IOH I P0 3 Integrating input 24 IOH I P0 1 Integrating input CP Power Vs...

Page 10: ...clock input EXTCLK 15 IOHR I P1 6 16 RESET INPUT XRES Active high external reset with internal pull down 17 IOH I P0 0 18 IOH I P0 2 19 IOH I P0 4 20 IOH I P0 6 21 IOH I P0 7 22 IOH I P0 5 23 IOH I P0 3 Integrating input 24 IOH I P0 1 Integrating input CP Power VSS Thermal pad must be connected to Ground LEGEND I Input O Output OH 5 mA High Output Drive R Regulated Output P0 7 I2C SDA SPI MISO P1 ...

Page 11: ...reset with internal pull down 18 IO I P3 0 19 IO I P3 2 20 IO I P2 0 21 IO I P2 2 22 IO I P2 4 23 IO I P2 6 24 IOH I P0 0 25 IOH I P0 2 26 IOH I P0 4 27 IOH I P0 6 28 Power Vdd Supply voltage 29 IOH I P0 7 30 IOH I P0 5 31 IOH I P0 3 Integrating input 32 Power Vss Ground connection CP Power Vss Center pad must be connected to ground LEGEND A Analog I Input O Output OH 5 mA High Output Drive R Regu...

Page 12: ...og Name Description 30 IO I P3 6 40 IOH I P0 6 31 IO I P4 0 41 Power Vdd Supply voltage 32 IO I P4 2 42 NC No connection 33 IO I P2 0 43 NC No connection 34 IO I P2 2 44 IOH I P0 7 35 IO I P2 4 45 IOH I P0 5 36 IO I P2 6 46 IOH I P0 3 Integrating input 37 IOH I P0 0 47 Power Vss Ground connection 38 IOH I P0 2 48 IOH I P0 1 39 IOH I P0 4 CP Power Vss Center pad must be connected to ground LEGEND A...

Page 13: ...27 IOHR IO P1 4 EXT CLK 28 IOHR IO P1 6 29 NC No connection 30 NC No connection 31 NC No connection 32 NC No connection Pin No Digital Analog Name Description 33 NC No connection 41 IO IO P2 2 34 NC No connection 42 IO IO P2 4 35 XRES Active high external reset with internal pull down 43 IO IO P2 6 36 IO IO P3 0 44 IOH IO P0 0 37 IO IO P3 2 45 IOH IO P0 2 38 IO IO P3 4 46 IOH IO P0 4 39 IO IO P3 6...

Page 14: ...l down 39 IOH I P0 4 27 IO I P3 0 40 IOH I P0 6 28 IO I P3 2 41 Power Vdd Supply voltage 29 IO I P3 4 42 OCDO OCD even data IO 30 IO I P3 6 43 OCDE OCD odd data output 31 IO I P4 0 44 IOH I P0 7 32 IO I P4 2 45 IOH I P0 5 33 IO I P2 0 46 IOH I P0 3 Integrating input 34 IO I P2 2 47 Power Vss Ground connection 35 IO I P2 4 48 IOH I P0 1 36 IO I P2 6 CP Power Vss Center pad must be connected to grou...

Page 15: ... Unit of Measure Symbol Unit of Measure C degree Celsius mA milli ampere dB decibels ms milli second fF femto farad mV milli volts Hz hertz nA nanoampere KB 1024 bytes ns nanosecond Kbit 1024 bits nV nanovolts kHz kilohertz Ω ohm ksps kilo samples per second pA picoampere kΩ kilohm pF picofarad MHz megahertz pp peak to peak MΩ megaohm ppm parts per million μA microampere ps picosecond μF microfara...

Page 16: ...ns Symbol Description Min Typ Max Units Conditions Input VIN Input Voltage Range Vss 1 3 V This gives 72 of maximum code CIN Input Capacitance 5 pF RES Resolution 8 10 Bits Settings 8 9 or 10 S8 8 Bit Sample Rate 23 4375 ksps Data Clock set to 6 MHz Sample Rate 0 001 2 Resolution Data clock S10 10 Bit Sample Rate 5 859 ksps Data Clock set to 6 MHz Sample Rate 0 001 2 Resolution Data clock DC Accur...

Page 17: ...e with JESD78 standard 200 mA Table 13 Operating Temperature Symbol Description Conditions Min Typ Max Units TA Ambient Temperature 40 85 C TJ Operational Die Temperature The temperature rise from ambient to junction is package specific Refer the table Thermal Impedances per Package on page 28 The user must limit the power consumption to comply with this requirement 40 100 C Table 14 DC Chip Level...

Page 18: ...tput Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH 10 μA Vdd 3 1V maximum of 4 IOs all sourcing 5 mA 2 85 3 00 3 3 V VOH6 High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH 5 mA Vdd 3 1V maximum of 20 mA source current in all IOs 2 20 V VOH7 High Output Voltage Port 1 Pins with LDO Enabled for 2 5V Out IOH 10 μA Vdd 2 7V maximum of 20 mA source current in all...

Page 19: ...A sink current on even port pins for example P0 2 and P1 4 and 30 mA sink current on odd port pins for example P0 3 and P1 5 0 75 V VIL Input Low Voltage 0 72 V VIH Input High Voltage 1 4 V VH Input Hysteresis Voltage 80 mV IIL Input Leakage Absolute Value 0 001 1 μA CPIN Capacitive Load on Pins Package and pin dependent Temp 25oC 0 5 1 7 5 pF Table 17 1 71V to 2 4V DC GPIO Specifications Symbol D...

Page 20: ... kΩ Rusba USB D Pull Up Resistance While receiving traffic 1 425 3 090 kΩ Vohusb Static Output High 2 8 3 6 V Volusb Static Output Low 0 3 V Vdi Differential Input Sensitivity 0 2 V Vcm Differential Input Common Mode Range 0 8 2 5 V Vse Single Ended Receiver Threshold 0 8 2 0 V Cin Transceiver Capacitance 50 pF Iio Hi Z State Data Line Leakage On D or D line 10 10 μA Rps2 PS 2 Pull Up Resistance 3...

Page 21: ...ter than 50 mV above VPPOR2 voltage for falling supply 8 Always greater than 50 mV above VPPOR3 voltage for falling supply 9 Always greater than 50 mV above VPPOR0 voltage for falling supply Table 22 DC Programming Specifications Symbol Description Conditions Min Typ Max Units VddIWRITE Supply Voltage for Flash Write Operations 1 71 V IDDP Supply Current During Programming or Verify 5 25 mA VILP I...

Page 22: ...Hz DCIMO Duty Cycle of IMO 40 50 60 TRAMP Supply Ramp Time 0 μs TXRST External Reset Pulse Width at Power Up After supply voltage is valid 1 ms TXRST2 External Reset Pulse Width after Power Up Applies after part has booted 10 μs Table 24 AC GPIO Specifications Symbol Description Conditions Min Typ Max Units FGPIO GPIO Operating Frequency Normal Strong Mode Port 0 1 0 0 6 MHz for 1 71V Vdd 2 4V 12 ...

Page 23: ...dj1 Driver differential jitter To next transition 3 5 3 5 ns Tudj2 Driver differential jitter To pair transition 4 0 4 0 ns Tfdeop Source jitter for differential transition To SE0 transition 2 5 ns Tfeopt Source SE0 interval of EOP 160 175 ns Tfeopr Receiver SE0 interval of EOP 82 ns Tfst Width of SE0 interval during differential transition 14 ns Table 26 AC Characteristics USB Driver Symbol Descr...

Page 24: ... 25 2 MHz High Period 20 6 5300 ns Low Period 20 6 ns Power Up IMO to Switch 150 μs Table 30 AC Programming Specifications Symbol Description Conditions Min Typ Max Units TRSCLK Rise Time of SCLK 1 20 ns TFSCLK Fall Time of SCLK 1 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 ns THSCLK Data Hold Time from Falling Edge of SCLK 40 ns FSCLK Frequency of SCLK 0 8 MHz TERASEB Flash Erase Tim...

Page 25: ... Description Standard Mode Fast Mode Units Min Max Min Max FSCLI2C SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time repeated START Condition After this period the first clock pulse is generated 4 0 0 6 μs TLOWI2C LOW Period of the SCL Clock 4 7 1 3 μs THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 μs TSUSTAI2C Setup Time for a Repeated START Condition 4 7 0 6 μs THDDATI2C Data Hold Time 0 0 ...

Page 26: ...the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions refer to the document titled PSoC Emulator Pod Dimensions at http www cypress com design MR10161 Figure 14 16 Pin Chip On Lead 3x3 mm Sawn Figure 15 24 Pin 4x4 x 0 6 mm QFN 001 09116 D 001 13937 B F...

Page 27: ...OTTOM VIEW TOP VIEW SIDE VIEW 3 PACKAGE WEIGHT 0 0388g 001 42168 LQ32 C COMPANY CONFIDENTIAL CYPRESS TITLE SIZE PART NO DWG NO REV SEE NOTE 1 32L QFN 5 X 5 X 0 55 MM PACKAGE OUTLINE 3 5 X 3 5 EPAD SAWN TYPE A 001 42168 C 51 85061 C 0 095 0 025 0 008 SEATING PLANE 0 420 0 088 020 0 292 0 299 0 395 0 092 BSC 0 110 0 016 0 620 0 008 0 0135 0 630 DIMENSIONS IN INCHES MIN MAX 0 040 0 024 0 8 GAUGE PLAN...

Page 28: ... 33 Thermal Impedances per Package Package Typical θJA 11 16 QFN 32 69oC W 24 QFN 12 20 90oC W 32 QFN 12 19 51oC W 48 SSOP 69oC W 48 QFN 12 17 68oC W Table 34 Solder Reflow Peak Temperature Package Minimum Peak Temperature 13 Maximum Peak Temperature 16 QFN 240oC 260oC 24 QFN 240oC 260oC 32 QFN 240oC 260oC 48 SSOP 220oC 260oC 48 QFN 240oC 260oC Notes 11 TJ TA Power x θJA 12 To achieve the thermal ...

Page 29: ... com ImageCraft Cypress Edition Compiler is available from http www imagecraft com Development Kits All development kits are sold at the Cypress Online Store CY3215 DK Basic Development Kit The CY3215 DK is for prototyping and development with PSoC Designer This kit supports in circuit emulation and the software interface enables users to run halt and single step the processor and view the content...

Page 30: ...8C24794 24LFXI PSoC device Special features of the board include both USB and capacitive sensing development and debugging support This evaluation board also includes an LCD module potentiometer LEDs an enunciator and plenty of bread boarding space to meet all of your evaluation needs The kit includes PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example P...

Page 31: ...KXI 16 QFN CY3250 20266QFN CY3250 16QFN RK See note 15 CY8C20336 24LQXI 24 QFN CY3250 20366QFN CY3250 20366QFN See note 15 CY8C20436 24LQXI 32 QFN CY3250 20466QFN CY3250 32QFN RK See note 15 CY8C20396 24LQXI Not Available CY8C20246 24LKXI 16 QFN CY3250 20266QFN CY3250 16QFN FK See note 16 CY8C20346 24LQXI 24 QFN CY3250 20366QFN CY3250 24QFN FK See note 16 CY8C20446 24LQXI 32 QFN CY3250 20466QFN CY...

Page 32: ...C20396 24LQXIT 16K 2K 1 19 19 Yes Yes 16 Pin 3x3 x 0 6 mm QFN CY8C20246 24LKXI 16K 2048 1 13 13 17 Yes No 16 Pin 3x3 x 0 6 mm QFN Tape and Reel CY8C20246 24LKXIT 16K 2048 1 13 13 17 Yes No 24 Pin 4x4 x 0 6 mm QFN CY8C20346 24LQXI 16K 2048 1 20 20 17 Yes No 24 Pin 4x4 x 0 6 mm QFN Tape and Reel CY8C20346 24LQXIT 16K 2048 1 20 20 17 Yes No 32 Pin 5x5 x 0 6 mm QFN CY8C20446 24LQXI 16K 2048 1 28 28 17...

Page 33: ... operating voltage ranges with USB ADC resolution changed from 10 bit to 8 bit Included ADC specifications table Included Comparator specification table Included Voh7 Voh8 Voh9 Voh10 specs Flash data retention condition added to Note Input leakage spec changed to 1 μA max GPIO rise time for ports 0 1 and ports 2 3 made common AC Programming specifications updated Included AC Programming cycle timi...

Page 34: ...ARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as c...

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