Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
Document No. 001-94024 Rev.*A
7
In the above scheme, RT=50
W
derives the RTT value:
shows a simple termination scheme that is
sometimes employed when there is a very short trace
length, but is not always recommended.
Figure 17. Simple LVPECL Termination Scheme
Z=50
W
Z=50
W
RT
RT
In the above scheme, RT=150
W
Note
VDD=1.8 V is not applicable for LVPECL standard.
LVDS Output Standard
LVDS signaling standard is also a differential I/O standard
and is defined by TIA/EIA-644-A (JEDEC standard) and its
typical termination is shown in
Figure 18. LVDS Signaling Termination (2.5 V, 3.3 V)
Z=50
W
Z=50
W
RT
VDD=2.5, 3.3V
Outputs (OUTxP and OUTxN) should be connected
together through a 100-
Ω resistor (RT=100
W
.
For VDD=1.8 V operation, you require AC coupling
(100-nF series capacitor) and bias at the destination using
termination resistors.
scheme.
Figure 19. LVDS Signaling Termination (1.8 V)
Z=50
W
Z=50
W
RT
VDD=1.8V
RP
RD
In the above scheme, RT=100
W
RP and RD must be chosen to meet VCM (common-mode
voltage) of 1.2 V (Typical).
CML Output Standard
CML interface is a differential I/O standard and is defined
in IEEE 802.3 spec.
scheme of this standard.
Figure 20. CML Signaling Termination
Z=50
W
Z=50
W
RT
RT
In the above figure, RT=50
W
and should be terminated to
VDD.
Using Differential Output as LVCMOS
The CY27410 device is highly flexible, enabling the use of
differential outputs in single-ended mode. Figure 21
illustrates the same: OUTxP and OUTxN should be tied
together for LVCMOS output.
Figure 21. Using Differential Output as LVCMOS standard
RS
C
LOAD
RS
should
be
chosen
for
impedance
matching
appropriately.
C
LOAD
represents the capacitive load of entire circuits.
Additional Features
CY27410 supports additional features like early/late output
phase synchronization circuit, voltage controller frequency
shift (VCFS), spread spectrum clock generator (SSCG)
and cascading PLLs.
Phase Delay of Outputs
Outputs of CY27410 can be configured to introduce a
certain delay in the outputs. This feature can be used in
both CLOCKGEN and ZDB mode. This feature is provided
as some ASIC and SoCs require fixed delay between 2
clocks.
The following equation derives one period unit for delay
circuit:
Wherein t
DL
=1 delay unit
Example: If f
VCO
=3.0 GHz, t
DL
= 0.666 ns
shows an example of a conceptual delay circuit.
