Document No. 001-94024 Rev.*A
1
AN94024
Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
Author: Hiromu Takehara, Jeetendra Ashok, Amitava Banerjee
Associated Project: No
Associated Part Family: CY27410
Software Version: N/A
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Cypress’s latest-generation high-performance clock generator device – CY27410 - is a 4-PLL, 12-output PCIe 3.0-
compliant device that provides a host of value-added features. This application note describes how to configure the
device in both clock generator and buffer modes with details on input/output standards, external design considerations,
reference selection including crystal, and the internal memory structure.
Contents
Contents ............................................................................ 1
Overview ........................................................................... 2
Key Specifications ............................................................. 2
Modes of Operation ........................................................... 2
CLKGEN Mode ............................................................. 2
ZDB Mode .................................................................... 3
NZDB Mode .................................................................. 3
Input Subsystem ............................................................... 3
Choosing the Crystal .................................................... 4
Input Reference Block ....................................................... 4
Input Frequency Tolerance ........................................... 4
Input Circuitry ............................................................... 4
Input Reference System ............................................... 5
Differential Input Signals............................................... 5
LVCMOS Input Signal .................................................. 5
Clipped Sine Wave Signal ............................................ 5
Output Subsystem ............................................................. 6
Output Termination............................................................ 6
HCSL Output Standard ................................................ 6
LVPECL Output Standard ............................................ 6
LVDS Output Standard ................................................. 7
CML Output Standard .................................................. 7
Using Differential Output as LVCMOS ......................... 7
Additional Features ........................................................... 7
Phase Delay of Outputs................................................ 7
Voltage-Controlled Frequency Shift (VCFS) ................. 8
Cascading PLLs ........................................................... 9
SSCG (Spread-Spectrum Clock Generator) ................. 9
Power-Up Sequence .................................................. 10
Power Supply Ramp ................................................... 10
Frequency Select (FS) ............................................... 10
Power Ramp Considerations ...................................... 10
Internal Memory Structure .......................................... 11
Programming CY27410 .............................................. 11
Conclusion ...................................................................... 11
Document History ............................................................ 12
Worldwide Sales and Design Support ............................. 13
Products .......................................................................... 13
PSoC® Solutions ............................................................ 13
Cypress Developer Community....................................... 13
Technical Support ........................................................... 13
