Cypress AN94024, Getting Started, Page: 4 / 13

Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
www.cypress.com
Document No. 001-94024 Rev.*A 4
Choosing the Crystal
CY27410 supports a crystal input between 8 MHz and
48 MHz. The equivalent crystal circuit with components is
shown in
Figure 5 .
Figure 5. Equivalent Crystal Circuit with L-R-C
Components
C0
R1 C1 L1
C0 = Crystal Shunt Capacitance
C1 = Crystal Motional Capacitance
R1 = Equivalent series Resistance
For CY27410, we recommend a crystal with parameters
as shown in the
Table 2 .
Table 2. Equivalent Resistance and Shunt Capacitance for
Values for Crystal
Nominal Frequency (in MHz) R1 (MAX) CL (pF)
8 to 12 150 ohms 8 to12
12 to 20 70 ohms 8 to12
20 to 48 50 ohms 8 to12
CL for All ranges Associated Max C0 (pF)
8 2
9 2
10 2
12 3
CY27410 Crystal oscillator circuit implements a low-power
(up to 100 micro watt drive level) and high-precision buffer
so that the crystal selection is important. Layout designers
are advised to keep the trace length between CY27410
and crystal as short as possible, and not to route any
active signal around the trace and crystal.
Input Reference Block
This section describes how to interface the input reference
signals to CY27410 and design considerations for input
signals.
Input Frequency Tolerance
The CY27410 design incorporates a narrow-
b
andwidth,
high-performance, low-noise PLL. The device cannot track
input clock tolerance more than 300 ppm. As a result, the
ceramic resonator that would vary in order of 1000s of
ppm cannot be used as a reference crystal. Also, spread-
spectrum clocks cannot be used as inputs to CY27410.
Input Circuitry
Figure 6 shows the input structure for the CY27410 device.
Figure 6. Input Structure for CY27410
IN_P
CMOS
Bias
ON: SE
OFF: DE
IN_N
VT
VLD-VT
LDO
VLD
VDD 2.5-3.3
TO: Internal Reference
VDD 1.8
When the single-ended (LVCMOS) configuration is
selected, both IN_P and IN_N pins are pulled down to
GND, and the AC coupled input signal is fed to P-N-
transistors shown above. Both P- and N- transistors are
then biased as fixed level (VLD-VT and VT). This voltage
difference provides enough margins for noisy inputs and
act with small input amplitude defined in the datasheet,
such as 0.8 Vp-p for clipped sine wave.
Input P-N- transistors are high-voltage (5 V) tolerant. You
may apply the input voltage more than the VDD, even
though VDD core supply is 1.8 V.
When DE (differential) input is selected, both IN_P and
IN_N are biased to certain level (1.2 V typical).