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STK15C88

256 Kbit (32K x 8) PowerStore nvSRAM

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document Number: 001-50593 Rev. **

 Revised January 29, 2009

Features

25 ns and 45 ns access times

Pin compatible with industry standard SRAMs

Automatic nonvolatile STORE on power loss

Nonvolatile STORE under Software control

Automatic RECALL to SRAM on power up

Unlimited Read/Write endurance

Unlimited RECALL cycles

1,000,000 STORE cycles 

100 year data retention 

Single 5V+10% power supply

Commercial and Industrial Temperatures

28-pin (300 mil and 330 mil) SOIC packages

RoHS compliance

Functional Description

The Cypress STK15C88 is a 256Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap

 technology

producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations are also
available under software control. 

PowerStore nvSRAM products depend on the intrinsic system
capacitance to maintain system power long enough for an
automatic store on power loss. If the power ramp from 5 volts
to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88
for more reliable operation.

  

Logic Block Diagram

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Summary of Contents for STK15C88

Page 1: ... with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automa...

Page 2: ...Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS...

Page 3: ...L to complete If the STK15C88 is in a WRITE state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The STK15C88 software STORE cycle is initiated by executing sequ...

Page 4: ... TTL input levels 5 The operating temperature 6 The VCC level 7 IO loading Figure 2 Current Versus Cycle Time WRITE Figure 3 Current Versus Cycle Time READ Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applica tions has resulted in the following suggestions as best ...

Page 5: ...Output Data Output Data 1 2 L H 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output Data 1 2 Notes 1 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 2 While there are 15 ...

Page 6: ... 100 70 mA mA ICC2 Average VCC Current during STORE All Inputs Do Not Care VCC Max Average current for duration tSTORE 3 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ICC4 Average Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for dur...

Page 7: ... following table the thermal resistance parameters are listed 4 Parameter Description Test Conditions 28 SOIC 300 mil 28 SOIC 330 mil Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 4 AC Test Loads AC Test Conditions 5 0V ...

Page 8: ...hip Disable to Output Inactive 10 15 ns tLZOE 7 tGLQX Output Enable to Output Active 0 0 ns tHZOE 7 tGHQZ Output Disable to Output Inactive 10 15 ns tPU 4 tELICCH Chip Enable to Power Active 0 0 ns tPD 4 tEHICCL Chip Disable to Power Standby 25 45 ns Switching Waveforms Figure 5 SRAM Read Cycle 1 Address Controlled 5 7 Figure 6 SRAM Read Cycle 2 CE and OE Controlled 5 W5 W W2 5 66 4 7 287 7 9 5 66...

Page 9: ...s Setup to Start of Write 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 7 8 tWLQZ Write Enable to Output Disable 10 15 ns tLZWE 7 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 7 SRAM Write Cycle 1 WE Controlled 8 Figure 8 SRAM Write Cycle 2 CE Controlled 8 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH I...

Page 10: ...on 10 ms VRESET Low Voltage Reset Level 3 6 V VSWITCH Low Voltage Trigger Level 4 0 4 5 V Switching Waveforms Figure 9 AutoStore Power Up RECALL 9 96 7 95 6 7 32 5 83 5 4 7 287 XWR6WRUH 9 W 5 W6725 32 5 83 5 52 1 287 XWR6WRUH 12 5 9 127 2 2 95 6 7 52 1 287 XWR6WRUH 5 1 9 5 78516 29 96 7 52 1 287 12 6725 8 72 12 65 0 5 7 6 12 5 9 127 2 2 95 6 7 Notes 10 tHRECALL starts from the time VCC rises above...

Page 11: ... tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 μs Switching Waveforms Figure 10 CE Controlled Software STORE RECALL Cycle 12 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 11 The software sequence is clocked on the falling edge of CE without involving OE double clocking will abort the sequence ...

Page 12: ...Commercial STK15C88 NF45 51 85026 28 Pin SOIC 300 mil STK15C88 SF45TR 51 85058 28 Pin SOIC 330 mil STK15C88 SF45 51 85058 28 Pin SOIC 330 mil STK15C88 NF45ITR 51 85026 28 Pin SOIC 300 mil Industrial STK15C88 NF45I 51 85026 28 Pin SOIC 300 mil STK15C88 SF45ITR 51 85058 28 Pin SOIC 330 mil STK15C88 SF45I 51 85058 28 Pin SOIC 330 mil All parts are Pb free The above table contains Final information Co...

Page 13: ...7 0 015 0 38 0 050 1 27 0 013 0 33 0 019 0 48 0 026 0 66 0 032 0 81 0 697 17 70 0 713 18 11 0 004 0 10 1 14 15 28 PART S28 3 STANDARD PKG SZ28 3 LEAD FREE PKG MIN MAX NOTE 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 3 DIMENSIONS IN INCHES 4 PACKAGE WEIGHT 0 85gms DOES INCLUDE MOL...

Page 14: ...STK15C88 Document Number 001 50593 Rev Page 14 of 15 Figure 12 28 Pin 330 mil SOIC 51 85058 Package Diagrams continued 51 85058 A Feedback ...

Page 15: ...as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNE...

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