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Cypress Semiconductor STK14C88-3, Specification Sheet, Page: 11 / 17

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Cypress Semiconductor STK14C88-3 Specification Sheet Download Page 11

STK14C88-3

Document Number: 001-50592 Rev. **

Page 11 of 17

AutoStore or Power Up RECALL

Parameter

Alt

Description

STK14C88-3

Unit

Min

Max

t

HRECALL 

[15]

t

RESTORE 

Power up RECALL Duration

550

μ

s

t

STORE 

[16, 17]

t

HLHZ 

STORE Cycle Duration

10

ms

t

VSBL

[16]

Low Voltage Trigger (V

SWITCH

) to HSB low

300

ns

V

RESET

Low Voltage Reset Level

2.4

V

V

SWITCH

Low Voltage Trigger Level

2.7

2.95

V

t

DELAY

[16]

 

t

BLQZ

Time Allowed to Complete SRAM Cycle

1

μ

s

Switching Waveforms

Figure 11.  AutoStore/Power Up RECALL

WE

Notes

15. t

HRECALL 

starts from the time V

CC

 rises above V

SWITCH

.

16. CE and OE low and WE high for output behavior.
17. HSB is asserted low for 1us when V

CAP

 drops through V

SWITCH

. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no 

store will take place.

[+] Feedback 

Summary of Contents for STK14C88-3

Page 1: ...volatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at ...

Page 2: ...OW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB Whe...

Page 3: ... of an CE controlled WRITE Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation The STK14C88 3 can be powered in one of three storage opera tions During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin ...

Page 4: ... HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK14C88 3 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition VCC VRESET an internal RECALL request is latched When VCC once again exceeds the sense voltage of VSWITCH a RECALL cycle is au...

Page 5: ...on VCAP and VCC crosses VSWITCH on the way down the STK14C88 3 attempts to pull HSB LOW If HSB does not actually get below VIL the part stops trying to pull HSB LOW and aborts the STORE attempt Hardware Protect The STK14C88 3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage condi tions When VCAP VSWITCH all externally initiated STORE operations and ...

Page 6: ...to meet this requirement and not exceed the max VCAP value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger VCAP value to ensure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period Table 2 Hardware Mode Selec...

Page 7: ...tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 9 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for duration tSTORE 2 mA ISB1 7 Average VCC Current Standby Cycling TTL Input Levels tRC 35ns CE VIH tRC 45ns CE VIH Commercial 18 16 mA Industrial 19 17 m...

Page 8: ...ce In the following table the thermal resistance parameters are listed 8 Parameter Description Test Conditions 32 SOIC 32 PDIP Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 6 AC Test Loads AC Test Conditions 3 3V Output ...

Page 9: ...CE 11 tEHQZ Chip Disable to Output Inactive 13 15 ns tLZOE 11 tGLQX Output Enable to Output Active 0 0 ns tHZOE 11 tGHQZ Output Disable to Output Inactive 13 15 ns tPU 8 tELICCH Chip Enable to Power Active 0 0 ns tPD 8 tEHICCL Chip Disable to Power Standby 35 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 9 10 Figure 8 SRAM Read Cycle 2 CE and OE Controlled 9 W5 W W2 5 66 ...

Page 10: ...0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 11 12 tWLQZ Write Enable to Output Disable 13 15 ns tLZWE 11 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 13 14 Figure 10 SRAM Write Cycle 2 CE Controlled 13 14 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREVIOU...

Page 11: ... Low Voltage Reset Level 2 4 V VSWITCH Low Voltage Trigger Level 2 7 2 95 V tDELAY 16 tBLQZ Time Allowed to Complete SRAM Cycle 1 μs Switching Waveforms Figure 11 AutoStore Power Up RECALL WE Notes 15 tHRECALL starts from the time VCC rises above VSWITCH 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when VCAP drops through VSWITCH If an SRAM WRITE has not taken pl...

Page 12: ... 18 19 tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 μs Switching Waveforms Figure 12 CE Controlled Software STORE RECALL Cycle 19 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking will abort the seq...

Page 13: ...TK14C88 3 Unit Min Max tPHSB tHLHX Hardware STORE Pulse Width 15 ns tDHSB 16 20 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveforms Figure 13 Hardware STORE Cycle 3 6 Note 20 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 14: ...l STK14C88 3NF45 51 85127 32 pin SOIC STK14C88 3WF45 51 85018 32 pin PDIP STK14C88 3NF45ITR 51 85127 32 pin SOIC Industrial STK14C88 3NF45I 51 85127 32 pin SOIC STK14C88 3WF45I 51 85018 32 pin PDIP All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Packaging Option TR Tape and Reel Blank Tube Speed...

Page 15: ...SIONS IN INCHES MM MIN MAX 0 292 7 416 0 299 7 594 0 405 10 287 0 419 10 642 0 050 1 270 TYP 0 090 2 286 0 100 2 540 0 004 0 101 0 0100 0 254 0 006 0 152 0 012 0 304 0 021 0 533 0 041 1 041 0 026 0 660 0 032 0 812 0 004 0 101 REFERENCE JEDEC MO 119 PART S32 3 STANDARD PKG SZ32 3 LEAD FREE PKG 0 014 0 355 0 020 0 508 0 810 20 574 0 822 20 878 51 85127 A Feedback ...

Page 16: ...STK14C88 3 Document Number 001 50592 Rev Page 16 of 17 Figure 15 32 Pin 600 Mil PDIP 51 85018 Package Diagrams continued 3 4 0 3 3 3 8 51 85018 A Feedback ...

Page 17: ...as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNE...

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