STK16C88-3
Document Number: 001-50594 Rev. **
Page 9 of 14
Table 3. SRAM Write Cycle
Parameter
Description
35 ns
Unit
Min
Max
Cypress
Parameter
Alt
t
WC
t
AVAV
Write Cycle Time
35
ns
t
PWE
t
WLWH,
t
WLEH
Write Pulse Width
25
ns
t
SCE
t
ELWH,
t
ELEH
Chip Enable To End of Write
25
ns
t
SD
t
DVWH,
t
DVEH
Data Setup to End of Write
12
ns
t
HD
t
WHDX,
t
EHDX
Data Hold After End of Write
0
ns
t
AW
t
AVWH,
t
AVEH
Address Setup to End of Write
25
ns
t
SA
t
AVWL,
t
AVEL
Address Setup to Start of Write
0
ns
t
HA
t
WHAX,
t
EHAX
Address Hold After End of Write
0
ns
t
HZWE
[7,8]
t
WLQZ
Write Enable to Output Disable
13
ns
t
LZWE
[7]
t
WHQX
Output Active After End of Write
5
ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled
[9]
Figure 8. SRAM Write Cycle 2: CE Controlled
[9]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than V
IH
during address transitions.
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