Cypress Semiconductor Perform STK16C88-3 Manual Download Page 10

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STK16C88-3

Document Number: 001-50594 Rev. **

Page 10 of 14

AutoStorePlus or Power Up RECALL

Parameter

Alt

Description

STK16C88-3

Unit

Min

Max

HRECALL

[10]

RESTORE

Power up RECALL Duration

550

STORE

HLHZ

STORE Cycle Duration

stg

[4, 6]

Power-down AutoStore Slew Time to Ground

500

RESET

Low Voltage Reset Level

2.4

SWITCH

Low Voltage Trigger Level

2.7

2.95

Switching Waveforms

Figure 9. AutoStorePlus/Power Up RECALL

6:,7&+

5(6(7

32:(583

5(&$//

'4'$7$287

$XWR6WRUH

+5(&$//

VWJ

6725(

%52:1287

$XWR6WRUH3OXVH

5(&$//

','127*2

%(/2:9

5(6(7

%52:1287

$XWR6WRUH3OXVH

5(&$//

:+(1

5(78516

$%29(9

6:,7&+

32:(583

5(&$//

%52:1287

6725(

'8(72

1265$0:5,7(6

5(&$//

','127*2

%(/2:9

5(6(7

Notes

10. t

HRECALL

starts from the time V

rises above V

SWITCH

[+] Feedback

Summary of Contents for Perform STK16C88-3

Page 1: ...ndustrial Temperatures 28 pin 600 mil PDIP package RoHS compliance Functional Description The Cypress STK16C88 3 is a 256Kb fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resi...

Page 2: ... Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VS...

Page 3: ...once again exceeds the sense voltage of VSWITCH a RECALL cycle is automatically initiated and takes tHRECALL to complete If the STK16C88 3 is in a WRITE state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC Software STORE Data is transferred from the SRAM to the nonvo...

Page 4: ... versus TTL input levels 5 The operating temperature 6 The VCC level 7 IO loading Figure 3 Current Versus Cycle Time WRITE Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applica tions has resulted in the following suggestions as best practices The nonvolatile cells i...

Page 5: ...Output Data Output Data 1 2 L H 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output Data 1 2 Notes 1 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 2 While there are 15 ...

Page 6: ...l 52 mA ICC2 Average VCC Current during STORE All Inputs Do Not Care VCC Max Average current for duration tSTORE 3 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 8 mA ISB1 3 Average VCC Current Standby Cycling TTL Input Levels tRC 35ns CE VIH Commercial 18 mA Industrial 1...

Page 7: ...s are listed 4 Parameter Description Test Conditions 28 PDIP Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and proce dures for measuring thermal impedance per EIA JESD51 TBD C W ΘJC Thermal Resistance Junction to Case TBD C W Figure 4 AC Test Loads AC Test Conditions 3 3V Output 30 pF R1 317Ω R2 351Ω Input Pulse Levels 0 V to 3 V Input Rise and Fall T...

Page 8: ... tEHQZ Chip Disable to Output Inactive 13 ns tLZOE 7 tGLQX Output Enable to Output Active 0 ns tHZOE 7 tGHQZ Output Disable to Output Inactive 13 ns tPU 4 tELICCH Chip Enable to Power Active 0 ns tPD 3 4 tEHICCL Chip Disable to Power Standby 35 ns Switching Waveforms Figure 5 SRAM Read Cycle 1 Address Controlled 5 6 Figure 6 SRAM Read Cycle 2 CE and OE Controlled 5 W5 W W2 5 66 4 7 287 7 9 5 66 W5...

Page 9: ... Start of Write 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 ns tHZWE 7 8 tWLQZ Write Enable to Output Disable 13 ns tLZWE 7 tWHQX Output Active After End of Write 5 ns Switching Waveforms Figure 7 SRAM Write Cycle 1 WE Controlled 9 Figure 8 SRAM Write Cycle 2 CE Controlled 9 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREVIOUS D...

Page 10: ...ore Slew Time to Ground 500 ns VRESET Low Voltage Reset Level 2 4 V VSWITCH Low Voltage Trigger Level 2 7 2 95 V Switching Waveforms Figure 9 AutoStorePlus Power Up RECALL 9 96 7 95 6 7 32 5 83 5 4 7 287 XWR6WRUH 9 W 5 WVWJ W6725 52 1 287 XWR6WRUH3OXVH 12 5 9 127 2 2 95 6 7 52 1 287 XWR6WRUH3OXVH 5 1 9 5 78516 29 96 7 32 5 83 5 52 1 287 12 6725 8 72 12 65 0 5 7 6 12 5 9 127 2 2 95 6 7 Notes 10 tHR...

Page 11: ...Address Hold Time 20 ns tRECALL RECALL Duration 20 μs Switching Waveforms Figure 10 CE Controlled Software STORE RECALL Cycle 12 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 11 The software sequence is clocked on the falling edge of CE without involving OE double clocking will abort the sequence 12 The six co...

Page 12: ...cial STK16C88 3WF35I Industrial All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Speed 35 35 ns Package W Plastic 28 pin 600 mil DIP Part Numbering Nomenclature STK16C88 3W F 35 I Temperature Range Blank Commercial 0 to 70 C Lead Finish F 100 Sn Matte Tin I Industrial 40 to 85 C Feedback ...

Page 13: ...STK16C88 3 Document Number 001 50594 Rev Page 13 of 14 Package Diagrams Figure 11 28 Pin 600 Mil PDIP 51 85017 51 85017 B Feedback ...

Page 14: ...as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNE...

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