Cypress Semiconductor Perform STK14D88 Manual Download Page 16 | Manualshive

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STK14D88

Document Number: 001-52037 Rev. **

Page 16 of 17

Figure 15. 48-Pin (300 Mil) SSOP (51-85061)

Package Diagrams

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51-85061-*C

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Summary of Contents for Perform STK14D88

Page 1: ... element included with each memory cell The SRAM provides fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile storage cells when power loss is detected the STORE operation On power up data is automatically restored to the SRAM the RECALL operation Both STORE and RECALL operations are also available under so...

Page 2: ...al to the chip it will initiate a nonvolatile STORE operation A weak pull up resistor keeps this pin high if not connected Connection Optional VCAP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements VSS Power Supply Ground NC No Connect Unlabeled pins have no internal connections 48 Pin SSOP TOP VSS A14 A12 A7 A6 DQ0 ...

Page 3: ...Unit Notes Min Max Min Max ICC1 Average VCC Current 65 55 50 70 60 55 mA mA mA tAVAV 25ns tAVAV 35ns tAVAV 45ns Dependent on output loading and cycle rate Values obtained without output loads ICC2 Average VCC Current during STORE 3 3 mA All Inputs Don t Care VCC max Average current for duration of STORE cycle tSTORE ICC3 Average VCC Current at tAVAV 200ns 3V 25 C Typical 10 10 mA W V CC 0 2V All O...

Page 4: ... Specs tHZ tLZ tWLQZ tWHQZ tGLQX tGHQZ Capacitance Parameter 3 Description Test Conditions Max Unit Conditions CIN Input Capacitance TA 25 C f 1 MHz 7 pF ΔV 0 to 3V COUT Output Capacitance 7 pF ΔV 0 to 3V DC Characteristics continued VCC 2 7V 3 6V Symbol Parameter 2 Commercial Industrial Unit Notes Min Max Min Max Input Pulse Levels 0V to 3V Input Rise and Fall Times 5 ns Input and Output Timing R...

Page 5: ...ress Change or Chip Enable to Output Active 3 3 3 ns 7 tEHQZ 6 tHZ Address Change or Chip Disable to Output Inactive 10 13 15 ns 8 tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9 tGHQZ 6 tOHZ Output Disable to Output Inactive 10 13 15 ns 10 tELICCH 3 tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICCL 3 tPS Chip Disable to Power Standby 25 35 45 ns Figure 4 SRAM READ Cycle 1 Address Controlle...

Page 6: ...ress Set up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 tWLQZ 6 8 tWZ Write Enable to Output Disable 10 13 15 ns 21 tWHQX tOW Output Active after End of Write 3 3 3 ns Figure 6 SRAM WRITE Cycle 1 W Controlled 8 9 Figure 7 SRAM WRITE Cycle 2 E Controlled 8 9 DATA OUT E ADDRESS W DATA IN PREVIOUS DATA 12 tAVAV 13 tWHDX 19 tWHAX 13 tWLWH 18 tAVWL 17 tAVWH...

Page 7: ...4 VSWITCH Low Voltage Trigger Level 2 65 V 25 VCCRISE Vcc Rise Time 150 μs Figure 8 AutoStore POWER UP RECALL Note Read and Write cycles are ignored during STORE RECALL and while VCC is below VSWITCH 22 23 23 22 22 Notes 10 tHRECALL starts from the time VCC rises above VSWITCH 11 If an SRAM WRITE has not taken place since the last nonvolatile cycle no STORE will take place 12 Industrial Grade Devi...

Page 8: ...30 ns 29 tEHAX Address Hold Time 1 1 1 ns 30 tRECALL RECALL Duration 50 50 50 μs Figure 9 E and G Controlled Software STORE RECALL Cycle 14 DATA VALID HIGH IMPEDANCE ADDRESS 6 ADDRESS 1 DATA VALID 26 tAVAV DATA VALID DQ DATA E ADDRESS 23 30 tSTORE tRECALL 26 tAVAV 27 tAVEL 28 tELEH 29 tELAX Notes 13 The software sequence is clocked on the falling edge of E controlled READs 14 The six consecutive a...

Page 9: ...STK14D88 Unit Notes Standard Min Max 33 tSS Soft Sequence Processing Time 70 µs 16 17 Figure 11 Software Sequence Commands 33 33 Notes 15 Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete 16 This is the amount of time that it takes to take action on a soft sequence command Vcc power must remain high to effectively register command 17 Command...

Page 10: ...Output Data Output Data Active 18 19 20 L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Active 18 19 20 0x0FC0 Nonvolatile Store Output High Z ICC2 L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output D...

Page 11: ...citor connected to the VCAP pin This stored charge will be used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part will automatically disconnect the VCAP pin from VCC A STORE operation will be initiated with power provided by the VCAP capacitor Figure 12 shows the proper connection of the storage capacitor VCAP for automatic store operation R...

Page 12: ...cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites will sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content valu...

Page 13: ...id READ 5 Read Address 0x303F Valid READ 6 Read Address 0x03F8 AutoStore Disable The AutoStore can be re enabled by initiating an AutoStore Enable sequence A sequence of READ operations is performed in a manner similar to the software RECALL initiation To initiate the AutoStore Enable sequence the following sequence of E controlled or G controlled READ operations must be performed 1 Read Address 0...

Page 14: ...ore nvSRAM SSOP48 300 35 ns Commercial STK14D88 RF45 3V 32Kx8 AutoStore nvSRAM SSOP48 300 45 ns Commercial STK14D88 RF25TR 3V 32Kx8 AutoStore nvSRAM SSOP48 300 25 ns Commercial STK14D88 RF35TR 3V 32Kx8 AutoStore nvSRAM SSOP48 300 35 ns Commercial STK14D88 RF45TR 3V 32Kx8 AutoStore nvSRAM SSOP48 300 45 ns Commercial STK14D88 NF25I 3V 32Kx8 AutoStore nvSRAM SOP32 300 25 ns Industrial STK14D88 NF35I ...

Page 15: ...N INCHES MM MIN MAX 0 292 7 416 0 299 7 594 0 405 10 287 0 419 10 642 0 050 1 270 TYP 0 090 2 286 0 100 2 540 0 004 0 101 0 0100 0 254 0 006 0 152 0 012 0 304 0 021 0 533 0 041 1 041 0 026 0 660 0 032 0 812 0 004 0 101 REFERENCE JEDEC MO 119 PART S32 3 STANDARD PKG SZ32 3 LEAD FREE PKG 0 014 0 355 0 020 0 508 0 810 20 574 0 822 20 878 51 85127 A Feedback ...

Page 16: ...STK14D88 Document Number 001 52037 Rev Page 16 of 17 Figure 15 48 Pin 300 Mil SSOP 51 85061 Package Diagrams continued 51 85061 C Feedback ...

Page 17: ...it as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FI...

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