Cypress Semiconductor Perform CY7C1411BV18 Manual Download Page 22

Page: 22 / 30

CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Document Number: 001-07037 Rev. *D

Page 22 of 30

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

Input

Capacitance

= 25

C, f = 1 MHz, V

= 1.8V, V

DDQ

= 1.5V

CLK

Clock Input Capacitance

Output Capacitance

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Package

Unit

Thermal Resistance
(Junction to Ambient)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.

17.2

°C/W

Thermal Resistance
(Junction to Case)

3.2

°C/W

Figure 4. AC Test Loads and Waveforms

1.25V

0.25V

R = 50

5 pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

= 50

REF

= 0.75V

REF

= 0.75V

[22]

0.75V

Under
Test

0.75V

Device
Under
Test

OUTPUT

0.75V

REF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ =
250

(b)

RQ =
250

Note

22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250

, V

DDQ

= 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified I

and load capacitance shown in (a) of

AC Test Loads and Waveforms

[+] Feedback

Summary of Contents for Perform CY7C1411BV18

Page 1: ...ipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports to access the memory array The read port has dedicated data outputs to support the read opera tions and the write port has dedicated data inputs to support the write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus ...

Page 2: ...er Reg Reg Reg 16 20 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 20 8 CQ CQ DOFF Q 7 0 8 8 8 Write Reg Write Reg Write Reg C C 1M x 8 Array 1M x 8 Array 1M x 8 Array 8 CLK A 19 0 Gen K K Control Logic Address Register D 8 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 18 20 36 9 BWS 0 VREF Write Add Decode Write Reg 18 A 19 0 20 9 CQ CQ DOFF Q 8 0 9 9...

Page 3: ...0 VREF Write Add Decode Write Reg 36 A 18 0 19 18 CQ CQ DOFF Q 17 0 18 18 18 Write Reg Write Reg Write Reg C C 512K x 18 Array 512K x 18 Array 512K x 18 Array 512K x 18 Array 18 256K x 36 Array CLK A 17 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 72 18 144 36 BWS 3 0 VREF Write Add Decode Write Reg 72 A 17 0 18 25...

Page 4: ...D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1426BV18 4M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A WPS NC K NC 144M RPS A A CQ B NC NC NC A NC 288M K BWS0 A NC NC Q4 C NC NC NC VSS A NC A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VD...

Page 5: ... A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1415BV18 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q1...

Page 6: ... x 8 for CY7C1411BV18 4M x 9 4 arrays each of 1M x 9 for CY7C1426BV18 2M x 18 4 arrays each of 512K x 18 for CY7C1413BV18 and 1M x 36 4 arrays each of 256K x 36 for CY7C1415BV18 Therefore only 20 address inputs are needed to access the entire memory array of CY7C1411BV18 and CY7C1426BV18 19 address inputs for CY7C1413BV18 and 18 address inputs for CY7C1415BV18 These inputs are ignored when the app...

Page 7: ...D or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timings in the DLL turned off operation differs from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 KΩ or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode the device can...

Page 8: ... K clock rise Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks C and C or K and K when in single clock mode When the read port is deselected the CY7C1413BV18 first completes the pending read transactions Synchronous internal circuitry automatically tri states the outputs following the next rising edge of the positive output ...

Page 9: ... impedance matching with a tolerance of 15 is between 175Ω and 350Ω with VDDQ 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the QDR II CQ is referenced with respect to C and CQ is reference...

Page 10: ...e data portion of a write sequence CY7C1411BV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1413BV18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1411BV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1413BV18 only the upper byte D 17 ...

Page 11: ...itten into the device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the Data portion of a write sequence only the byte D 17 9 is...

Page 12: ...lling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset ...

Page 13: ...dary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE an...

Page 14: ...ontroller follows 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 11 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback ...

Page 15: ...ut HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 12 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load ...

Page 16: ... tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 16 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TM...

Page 17: ... Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z s...

Page 18: ...2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 ...

Page 19: ...clock K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide1024 cycles stable clock t...

Page 20: ...tput HIGH Voltage Note 18 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 0 3 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 5 5 μA IOZ Output Leakage Current ...

Page 21: ...tatic 300MHz x8 370 mA x9 370 x18 370 x36 400 278MHz x8 355 mA x9 355 x18 355 x36 370 250MHz x8 355 mA x9 355 x18 355 x36 370 200MHz x8 300 mA x9 300 x18 300 x36 300 167MHz x8 270 mA x9 270 x18 270 x36 270 AC Electrical Characteristics Over the Operating Range 13 Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF 0 2 V VIL Input LOW Voltage VREF 0 2 V Electrical Cha...

Page 22: ...nction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 17 2 C W ΘJC Thermal Resistance Junction to Case 3 2 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50Ω Z0 50Ω VREF 0 75V VREF 0 75V 22 0 75V Under Test 0 75V Device Under Test OUTPUT 0 75V VR...

Page 23: ...ise RPS WPS 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD 25 tDVKH D X 0 Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0 5 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 4 0 4 0 5 0 6 0 7 ns tHC tKHIX Control Hold after K Clock Rise RPS WPS 0 4 0 4 0 5 0 6 0 7 ns tHCDDR tKHIX Double Data Rate Control Hold ...

Page 24: ...gh Z 27 28 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 27 28 0 45 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 20 0 20 0 20 0 20 ns tKC lock tKC lock DLL Lock Time K C 1024 1024 1024 1024 1024 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns Switching Characteristics continued Over the Operating Range 22 23 Cypress Parameter Cons...

Page 25: ...CLZ DOH tCHZ t t tKL tCYC tCCQO t CCQO tCQOH tCQOH KHKH KH Q00 Q03 Q01 Q02 Q20 Q23 Q21 Q22 tCO tCQDOH t tCQH tCQHCQH D10 D11 D12 D13 t SD tHD tSD tHD D30 D31 D32 D33 Notes 29 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 that is A0 1 30 Outputs are disabled High Z one clock cycle after a NOP 31 In this example if address A2 A1 then data...

Page 26: ...Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1426BV18 300BZI CY7C1413BV18 300BZI CY7C1415BV18 300BZI CY7C1411BV18 300BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1426BV18 300BZXI CY7C1413BV18 300BZXI CY7C1415BV18 300BZXI 278 CY7C1411BV18 278BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1426BV18 278BZC CY7C1413B...

Page 27: ...BV18 250BZXI 200 CY7C1411BV18 200BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1426BV18 200BZC CY7C1413BV18 200BZC CY7C1415BV18 200BZC CY7C1411BV18 200BZXC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1426BV18 200BZXC CY7C1413BV18 200BZXC CY7C1415BV18 200BZXC CY7C1411BV18 200BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1...

Page 28: ...15BV18 167BZXC CY7C1411BV18 167BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1426BV18 167BZI CY7C1413BV18 167BZI CY7C1415BV18 167BZI CY7C1411BV18 167BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1426BV18 167BZXI CY7C1413BV18 167BZXI CY7C1415BV18 167BZXI Ordering Information continued Not all of the speed package and temperature ra...

Page 29: ...3BV18 CY7C1415BV18 Document Number 001 07037 Rev D Page 29 of 30 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G 2 2 3 0 51 85195 A Feedback ...

Page 30: ...TNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expect...

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