Cypress Semiconductor Perform CY7C1392CV18 Manual Download Page 23

Page: 23 / 30

CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C

Page 23 of 30

Switching Characteristics

Over the Operating Range

[20, 21]

Cypress

Parameter

Consortium

Parameter

Description

300 MHz

278 MHz

250 MHz

200 MHz

167 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

POWER

(Typical) to the First Access

[22]

CYC

KHKH

K Clock and C Clock Cycle Time

3.3

8.4

3.6

8.4

4.0

8.4

5.0

8.4

6.0

8.4

KHKL

Input Clock (K/K; C/C) HIGH

1.32

–

1.4

–

1.6

–

2.0

–

2.4

–

KLKH

Input Clock (K/K; C/C) LOW

1.32

–

1.4

–

1.6

–

2.0

–

2.4

–

KHKH

K Clock Rise to K Clock Rise and C
to C Rise (rising edge to rising edge)

1.49

–

1.6

–

1.8

–

2.2

–

2.7

–

KHCH

K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)

1.45

1.55

1.8

2.2

2.7

Setup Times

AVKH

Address Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

IVKH

Control Setup to K Clock Rise
(LD, R/W)

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

SCDDR

IVKH

Double Data Rate Control Setup to
Clock (K/K) Rise
(BWS

, BWS

BWS

, BWS

)

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

[23]

DVKH

[X:0]

Setup to Clock (K/K) Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

Hold Times

KHAX

Address Hold after K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

KHIX

Control Hold after K Clock Rise
(LD, R/W)

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

HCDDR

KHIX

Double Data Rate Control Hold after
Clock (K/K) Rise
(BWS

, BWS

)

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

KHDX

[X:0]

Hold after Clock (K/K) Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

Notes

21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

22. This part has a voltage regulator internally; t

POWER

is the time that the power must be supplied above V

minimum initially before a read or write operation can be

initiated.

23. For D2 data signal on CY7C1992CV18 device, t

is 0.5 ns for 200 MHz, 250 MHz, 278 MHz, and 300 MHz frequencies.

[+] Feedback

Summary of Contents for Perform CY7C1392CV18

Page 1: ...rray The read port has data outputs to support read operations and the write port has data inputs to support write operations The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to turn around the data bus required with common IO devices Access to each port is accomplished through a common address bus Addresses for read and write are latched on alternate risin...

Page 2: ...dd Decode Read Data Reg LD Q 7 0 Reg Reg Reg 8 8 16 8 NWS 1 0 VREF Write Add Decode Write Data Reg 8 8 20 8 R W LD R W CQ CQ DOFF 1M x 8 Array Write Data Reg Control Logic C C 1M x 9 Array CLK A 19 0 Gen K K Control Logic Address Register D 8 0 Read Add Decode Read Data Reg LD Q 8 0 Reg Reg Reg 9 18 9 BWS 0 VREF Write Add Decode Write Data Reg 9 9 20 9 R W LD R W CQ CQ DOFF 1M x 9 Array Write Data...

Page 3: ...ead Data Reg LD Q 17 0 Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode Write Data Reg 18 18 19 18 R W LD R W CQ CQ DOFF 512K x 18 Array Write Data Reg Control Logic C C 18 256K x 18 Array CLK A 17 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg LD Q 35 0 Reg Reg Reg 36 72 36 BWS 3 0 VREF Write Add Decode Write Data Reg 36 36 18 36 R W LD R W CQ CQ DOFF 256K x 18 Ar...

Page 4: ... VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1992CV18 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A R W NC K NC 144M LD A NC 36M CQ B NC NC NC A NC 288M K BWS0 A NC NC Q4 C NC NC NC VSS A A A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ N...

Page 5: ...NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1394CV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M R W BWS2 K BWS1 LD NC 36M NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q1...

Page 6: ...rations Internally the device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1392CV18 2M x 9 2 arrays each of 1M x 9 for CY7C1992CV18 1M x 18 2 arrays each of 512K x 18 for CY7C1393CV18 and 512K x 36 2 arrays each of 256K x 36 for CY7C1394CV18 Therefore only 20 address inputs are needed to access the entire memory array of CY7C1392CV18 and CY7C1992CV18 19 address inputs for CY7C1393CV18 an...

Page 7: ...nected DOFF Input DLL turn off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the DLL turned off operation differs from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 Kohm or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated a...

Page 8: ...egister provided BWS 1 0 are both asserted active The 36 bits of data are then written into the memory array at the specified location Write accesses can be initiated on every rising edge of the positive input clock K This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When Write access is deselected the device ...

Page 9: ... ns However it is not necessary to reset the DLL to lock it to the desired frequency The DLL automatically locks 1024 clock cycles after a stable clock is presented The DLL may be disabled by applying ground to the DOFF pin When the DLL is turned off the device behaves in DDR I mode with one cycle latency and a longer access time For information refer to the application note DLL Considerations in ...

Page 10: ...tten into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1392CV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1393CV18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1392CV18 only the upper nibble D 7 4 is written into the device...

Page 11: ...n into the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is wri...

Page 12: ...g edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset stat...

Page 13: ...y scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and P...

Page 14: ...troller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback ...

Page 15: ...HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load lev...

Page 16: ...IH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 14 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TMS Te...

Page 17: ...truction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state...

Page 18: ... 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 11C 71 1D 99 2P 16 9N 44 9B 72 2C 100 1P 17 11L 45 10B 73 3E 101 3R 18 11M 46 11A 74 2D 102 4R 19 9L 47 Internal 75 2E 103 4P 20 10L 48 9A 76 1E 104 5P 21 11K 49 8B 77 2F 105 5N 22 10K ...

Page 19: ...k K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide1024 cycles stable clock to re...

Page 20: ... Output HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 3 V VIL Input LOW Voltage 0 3 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 5 5 μA IOZ Output Leakage Curren...

Page 21: ... 300 MHz x8 275 mA x9 275 x18 285 x36 300 278 MHz x8 265 mA x9 265 x18 275 x36 290 250 MHz x8 255 mA x9 255 x18 260 x36 275 200 MHz x8 245 mA x9 245 x18 250 x36 260 167 MHz x8 240 mA x9 240 x18 245 x36 255 AC Electrical Characteristics Over the Operating Range 11 Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF 0 2 V VIL Input LOW Voltage VREF 0 2 V Electrical Cha...

Page 22: ...on to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 18 7 C W ΘJC Thermal Resistance Junction to Case 4 5 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device RL 50Ω Z0 50Ω VREF 0 75V VREF 0 75V 20 0 75V Under Test 0 75V Device Under Test OUTPUT 0 75V VREF V...

Page 23: ...e LD R W 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD 23 tDVKH D X 0 Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0 5 ns Hold Times tHA tKHAX Address Hold after K Clock Rise 0 4 0 4 0 5 0 6 0 7 ns tHC tKHIX Control Hold after K Clock Rise LD R W 0 4 0 4 0 5 0 6 0 7 ns tHCDDR tKHIX Double Data Rate Control Hold afte...

Page 24: ... 25 26 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 25 26 0 45 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 20 0 20 0 20 0 20 ns tKC lock tKC lock DLL Lock Time K C 1024 1024 1024 1024 1024 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns Switching Characteristics continued Over the Operating Range 20 21 Cypress Parameter Consorti...

Page 25: ... tHA tSD tHD tSD tHD tCLZ tDOH SC tKH tKHKH tKL tCYC tCQD tCCQO tCQOH tCCQO tCQOH DON T CARE UNDEFINED A0 A1 A2 A3 A4 D20 D21 D30 D31 Q40 Q11 Q10 Q41 Q00 Q01 tCQDOH tCQH tCQHCQH tCHZ Notes 27 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 that is A0 1 28 Outputs are disabled High Z one clock cycle after a NOP 29 In this example if addres...

Page 26: ... Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1992CV18 300BZI CY7C1393CV18 300BZI CY7C1394CV18 300BZI CY7C1392CV18 300BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1992CV18 300BZXI CY7C1393CV18 300BZXI CY7C1394CV18 300BZXI 278 CY7C1392CV18 278BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1992CV18 278BZC CY7C1393CV18 ...

Page 27: ... 250BZXI 200 CY7C1392CV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1992CV18 200BZC CY7C1393CV18 200BZC CY7C1394CV18 200BZC CY7C1392CV18 200BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1992CV18 200BZXC CY7C1393CV18 200BZXC CY7C1394CV18 200BZXC CY7C1392CV18 200BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 m...

Page 28: ...18 167BZXC CY7C1392CV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1992CV18 167BZI CY7C1393CV18 167BZI CY7C1394CV18 167BZI CY7C1392CV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1992CV18 167BZXI CY7C1393CV18 167BZXI CY7C1394CV18 167BZXI Ordering Information continued Not all of the speed package and temperature ranges...

Page 29: ...B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A A 15 00 0 10 13 00 0 10 B C 1 00 5 00 0 36 0 06 0 14 1 40 MAX SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD NOTES PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE ...

Page 30: ...OSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant...

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