Cypress Semiconductor Perform CY62146E MoBL Manual Download Page 10 | Manualshive

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CY62146E MoBL

®

Document Number: 001-07970 Rev. *D

Page 10 of 11

Package Diagrams

Figure 10. 44-Pin TSOP II, 51-85087

51-85087-*A

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Summary of Contents for Perform CY62146E MoBL

Page 1: ...nd output pins IO0 through IO15 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH Write operation is active CE LOW and WE LOW To write to the device take Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from IO pins IO0 through IO7 is written into the loc...

Page 2: ...5 5 45 2 2 5 15 20 1 7 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 A5 18 17 20 19 27 28 25 26 22 21 23 24 A6 A7 A4 A3 A2 A1 A0 A15 A16 A8 A9 A10 A11 A13 A14 A12 OE BHE BLE CE WE IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 VCC VCC VSS VSS NC 10 A17 Notes 1 NC pins are not connected on the die 2 Typical values are included for referen...

Page 3: ...D VO VCC Output Disabled 1 1 μA ICC VCC Operating Supply Current f fmax 1 tRC VCC VCCmax IOUT 0 mA CMOS levels 15 20 mA f 1 MHz 2 2 5 ISB2 6 Automatic CE Power down Current CMOS Inputs CE VCC 0 2V VIN VCC 0 2V or VIN 0 2V f 0 VCC VCC max 1 7 μA Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions Max Unit CIN In...

Page 4: ...1 7 μA tCDR 7 Chip Deselect to Data Retention Time 0 ns tR 8 Operation Recovery Time tRC ns Figure 3 Data Retention Waveform VCC VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90 10 90 10 Rise Time 1 V ns Fall Time 1 V ns OUTPUT V Equivalent to THÉVENIN EQUIVALENT ALL INPUT PULSES RTH R1 TH Notes 7 Tested initially and after any design or process changes that may affect these parameters 8 Full de...

Page 5: ... Hold from Write End 0 ns tHZWE WE LOW to High Z 11 12 18 ns tLZWE WE HIGH to Low Z 11 10 ns Notes 9 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of 1 5V input pulse levels of 0 to 3V and output loading of the specified IOL IOH as shown in AC Test Loads and Waveforms on page 4 10 AC timing parameters ...

Page 6: ...ALID DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tLZBE tLZCE tPU HIGHIMPEDANCE ICC tHZOE tHZCE tPD tHZBE tLZOE tDBE tDOE IMPEDANCE HIGH ISB DATA OUT OE CE VCC SUPPLY CURRENT BHE BLE ADDRESS Notes 14 The device is continuously selected OE CE VIL BHE BLE or both VIL 15 WE is HIGH for read cycle 16 Address valid before or similar to CE BHE BLE transition LOW Feedback Feedbac...

Page 7: ...SA tHA tAW tWC tHZOE DATAIN NOTE 19 tBW tSCE DATA IO ADDRESS CE WE OE BHE BLE tHD tSD tPWE tHA tAW tSCE tWC tHZOE DATAIN tBW tSA CE ADDRESS WE DATA IO OE BHE BLE NOTE 19 Notes 17 Data IO is high impedance if OE VIH 18 If CE goes HIGH simultaneously with WE VIH the output remains in a high impedance state 19 During this period the IOs are in output state Do not apply input signals Feedback Feedback...

Page 8: ...E LOW 18 Figure 9 Write Cycle 4 BHE BLE Controlled OE LOW 18 Switching Waveforms continued DATAIN tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE tBW NOTE 19 CE ADDRESS WE DATA IO BHE BLE tHD tSD tSA tHA tAW tWC DATAIN tBW tSCE tPWE tHZWE tLZWE NOTE 19 DATA IO ADDRESS CE WE BHE BLE Feedback Feedback ...

Page 9: ...ive ICC L H H H L High Z Output Disabled Active ICC L H H L H High Z Output Disabled Active ICC L L X L L Data In IO0 IO15 Write Active ICC L L X H L Data In IO0 IO7 IO8 IO15 in High Z Write Active ICC L L X L H Data In IO8 IO15 IO0 IO7 in High Z Write Active ICC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 45 CY62146ELL 45ZSXI 51 85087 44 pin Thin Small...

Page 10: ...CY62146E MoBL Document Number 001 07970 Rev D Page 10 of 11 Package Diagrams Figure 10 44 Pin TSOP II 51 85087 51 85087 A Feedback Feedback ...

Page 11: ...ting custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY ...

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